Oscillator Flicker Phase Noise: A Tutorial

Hu, Yizhe; Siriburanon, Teerachot; Staszewski, Robert Bogdan

doi:10.1109/tcsii.2020.3043165

Cited by 33 publications

(31 citation statements)

References 76 publications

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“…The fine-tuning bank employs custom-made MOM caps, achieving a resolution of ∼80 kHz with 40 aF, which is around 10 ppm for 8 GHz. Different supply domains are employed for the Q-DCO's core and its sw-caps to eliminate any singled-ended capacitance in the sw-caps being seen as a CM capacitance, which improves the CM impedance and reduces 4kT g ds noise [44], [46], [47]. The I/Q mismatch can be calibrated easily by providing a bit different tuning codes between C D,fine in I and Q parts of the Q-DCO.…”

Section: Charge-sharing Switch With Adaptive Body-biasingmentioning

confidence: 99%

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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Section: Charge-sharing Switch With Adaptive Body-biasingmentioning

confidence: 99%

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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“…It was again because the case study was another form of an LC oscillator that was the complementary cross-coupled voltage-biased oscillator, illustrated in Figure 13. Later in 2020, Hu et al 53 demonstrate that both the odd and even harmonics of current have effects on the 1/f noise up-conversion.…”

Section: More On Isf Reductionmentioning

confidence: 99%

“…Surprisingly, however, the waveform symmetry is not the only method to suppress the 1/f noise up-conversion. 53 The next sections discuss other techniques for suppressing the 1/f noise up-conversion.…”

Section: More On Isf Reductionmentioning

confidence: 99%

“…One way is to use a tail inductor along with the decoupling capacitance, as exhibited in Figure 23. 3,42,47,53 Note that only the tank-current second harmonic is trapped; the other high-frequency harmonics still make the tank energy unbalanced. F I G U R E 2 2 A complementary voltage-biased oscillator that resistors are added in the drains of transistors 49 The other way is to use a tank, resonating at ω 0 , with auxiliary resonances at 2ω 0 , 3ω 0 , …, and so on.…”

Section: Modifying Tankmentioning

confidence: 99%

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Phase noise suppression in LC oscillators: Tutorial

Bagheri

2021

Circuit Theory & Apps

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This paper presents a comprehensive study of phase noise (PN) suppression in LC-tank oscillators. The goal of this study is to provide designers with the latest techniques for reducing PN in cross-coupled oscillators. To this end, we begin with a discussion of two prevalent PN models in oscillators: Hajimiri and Demir. We prefer the Hajimiri model because it does not involve very complicated math, and it offers engineers better insight into designing low-PN oscillators in the two-PN close-in regions in an oscillator spectrum (1/f 2 and 1/f 3 ). In 1/f 2 region, we show that a need for a large output-voltage swing leads to Class D and B oscillators, and a large output-current swing results in Class C oscillators. Also, reduction of the impulse sensitivity functions (ISFs) of an oscillator core can happen in Class F oscillators. A few solutions are presented for mitigating flicker noise up-conversion, such as adding resistances, controlling the oscillation amplitude, decreasing the conduction angle, guiding the high-frequency harmonics of current, and shifting the phase of V GS against V DS . We also provide a comparison of recent state-of-the-art literature to show what constitutes a good PN in both 1/f 2 and 1/f 3 regions in cross-coupled oscillators. We conclude that a cross-coupled oscillator can reach the best performances in 1/f 3 and 1/f 2 PN regions if the oscillator is designed in Class C with the K block and uses the techniques of narrowing the conduction angle, the tail inductor, and the modified tank simultaneously.

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“…Some transistors biased in the linear region are placed between the sources and the ground of the NMOS CC pair to implement two variable resistors, R 1 and R 2 , which decouple the two nodes and allow to fine tune the frequency through a modified version of the capacitive degeneration technique as explained in Section II-B. The contribution of R 1,2 to the total PN is assessed by getting their Impulse Sensitivity Function (ISF) and cyclostationary noise from simulation as shown in [11]. The latter simulations show that their impact is negligible compared to the CC pairs in the 1/f 3 and 1/f 2 regions.…”

Section: A Low Power and Low Voltage Oscillator Structurementioning

confidence: 99%

Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars

Chicco

Rengifo

Pengg

et al. 2021

IEEE Microw. Wireless Compon. Lett.

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This work presents the design of a 24 GHz DCO in an advanced 28-nm bulk CMOS technology for short-range Frequency-Modulated Continuous-Wave radar System-on-Chip for mobile and Internet-of-Things devices. The power minimization is therefore the primary focus. The oscillator consumes a record low power of 1.2 mW at a 0.65 V supply voltage. It achieves a very large frequency tuning range of 5.8 GHz (27%) and a 150 kHz resolution without significantly degrading the phase noise. The proposed design methodology results in a State-of-the-Art −193 dBc/Hz FoMT.

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Oscillator Flicker Phase Noise: A Tutorial

Cited by 33 publications

References 76 publications

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Phase noise suppression in LC oscillators: Tutorial

Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars

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