A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

Mahalingam, Nagarajan; Wang, Yisheng; Thangarasu, Bharatha Kumar; Ma, Kaixue; Yeo, Kiat Seng

doi:10.1109/tmtt.2017.2699671

Cited by 30 publications

(6 citation statements)

References 20 publications

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“…As shown in Figure 3, when the reference current is switched from 1.0 mA to 2.0 mA, the phase noise can be reduced by 6.4 dB, which agrees well with the theoretical value of 6.0 dB which is calculated according to (1). And the simulated FOM can be reduced by 3.4 dB according to (5). As shown in Figure 3, the switched current case has lower flicker noise and higher flicker noise corner, because the higher oscillation amplitude suppresses flicker noise and increases flicker noise corner as the bias current raises.…”

Section: Four-core Vco Arraysupporting

confidence: 85%

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X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.

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Section: Four-core Vco Arraysupporting

confidence: 85%

“…There are three kinds of PLL architectures 3 : PLL using a fundamental voltage-controlled oscillator (VCO), PLL using an N-push VCO, and PLL followed by a frequency multiplier. For the first one, [4][5][6][7] its frequency range depends on the tuning range of the VCO. In Ref.…”

Section: Introductionmentioning

confidence: 99%

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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“…The standard metrics for PLL performance quality are ℒnorm [16], FoM [1], and FoMJRP [21] described as follows: 20 log( ) 10 log( ) ISSCC'19 [22] ISSCC'20 [23] TMTT'17 [24] ISSCC'16 [25] TMTT'20 [26] ISSCC'19 [27] This work…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Liang

Boon

2022

IEEE Trans. Microwave Theory Techn.

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The high phase noise of CMOS millimeterwave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This paper proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the trade-off between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection as well as lock detection. Implemented in 40 nm CMOS technology, the proposed PLL shows a −75 dBc reference spur, -101.5 dBc/Hz phase noise at 1 MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 k -100 MHz) at 38.2 GHz, with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.

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“…The opti-mized DVGA with bandwidth extension is presented in [19]. An updated PLL synthesizer with power distribution network to provide LO signals to the transmitter and receiver chains at the same time is introduced and presented in [31]. The opti-mized matching network including high isolation switches for efficient power delivery both HD and FD modes is described in it.…”

Section: Design and Implementationmentioning

confidence: 99%

Full-Duplex 60GHz Transceiver with Digital Self-Interference Cancellation

Wang,

Thangarasu,

Mahalingam

et al. 2023

Preprint

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This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60GHz wireless communication system. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operation to deliver better channel utilization and faster response time for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operation has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60GHz system, a wide bandwidth baseband digital variable gain amplifier (DVGA) with a 3dB bandwidth of more than 4GHz also supports frequency division duplex (FDD) operation. The transceiver chip is fabricated in Tower Jazz 0.18µm SiGe BiCMOS process. With on-board antenna, the transceiver covers all four channels in 802.11ad standard with MCS-12 (7.04Gbps under 1.76GSym/s and 16-QAM) under 1.5m. In the proposed system design, the RF frontend based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54dB. To achieve a practical FD application, the SI is further suppressed with the help of digital SI compensation. The measured power consumption for transmitter and receiver configuration is 194mW and 231mW, respectively, in HD mode and 398mW for FDD or FD operation mode.

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A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

Cited by 30 publications

References 20 publications

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Full-Duplex 60GHz Transceiver with Digital Self-Interference Cancellation

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A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

Cited by 30 publications

References 20 publications

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Full-Duplex 60GHz Transceiver with Digital Self-Interference Cancellation

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Product

Resources

About

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector