A 30 MHz high-speed analog/digital PLL in 2 mu m CMOS

Abstract

This paper describes an analogi digital approach to data clock recovery which allows the implementation of a quasi digital PLL with an effective local clock fr equcncy of I GHz in 21lm CMOS. The large phase jumps normally associated with digital PLLs are avoided' .The basic concept of the clock recovery system is sho wn in Figure 1. A long ring oscillator (32 stages in this example) is per manently frequency-locked to a reference frequency at the data window rate, (the read clock in the case of a disk drive data sep arator). Since thc dynamics of this loop do not affect phase acquisilion or tracking, the design is non-critical. Each tap on the ring oscillator is used tD latch data samples into one of the 32 latches, so that at the end of one round trip (one bit lime) 32 sa mples spaced 1 gate delay apart are stored in the 32 data latches. In 21lm technulogy this gives an effective "mplr rate of IGHz. In 11lm it i. ab out JGllz. After SUbsequently being moved to a separate holding regis ter, the bit pattern is evaluated to determine the location of valid transitions in the data window using digital transition detectors of complexity appropriate to the application. Noise filtering is easily applied to eliminate the effects of isolated noise pulses and metastahility.PLL operation is purely digital and is based on the locatiun of detected transitiuns. The center of the curren t winduw is held in a current-phase tap register, and this register is updated by the digitally lowpass filtered phase error signal. The phase error signal is simply the difference in tap location bet ween th e current window center and the occurrence of a valid data transi tion. Zero phase start, variable loop lime constant, and other modes are implemented digitally. Other speciali7.ed disk drive function s, such as variable win do" width and offset, and pul se pail' ing compensation, can also be implemented directly in the digital domain.The most critical circuit issue in this approach to high-speed clock recovery is phase noise in the data-sampling process, whieh arises from a number of sources including ring oscillator phase noise due to the inherent thermal noise in the inverters them selves, noise due to power supply noise injection, and metasta bil ity in the lalehes med to sample the data.The first-order analysis of thermal noise accumulation in dicates that it is related to the thermal noise at the input of each inverter stage, inverter rise time, signal swing, and loop band.width. For a given technology and set of design parameters, the total effective mean-square thermal noise at the input of each in verter, when the inverter is in its active region, is related to v'kT le gs where C g a is the gate capacitance of the invert er stage. A sampling jilt�r of .07ns rms dictat�d the use of large devices (160/2) in the inverter chain from kT Ie noise considerations.A second major issue is coupling of supply noise. Tradi tionally, CMOS ring-oscillator-based PLLs have used starved in verters together with, for example, an on-chip regulator to ...

Analog-to-digital conversion via duty-cycle modulation

“…7 that the time moments of the zero crossings of the square wave coincide with the moments that the error signal crosses the hysteresis values and , so at at where is integer. Algebraic evaluation (Appendix I) after insertion of (5-3) into (5-2) shows that (5-1) is satisfied if and If is an ideal integrator (5)(6) Equations and evolve [12] to (5)(6)(7) and (5)(6)(7)(8) where…”

“…It is tempting to conclude that (5-7) and (5)(6)(7)(8) confirm that the asynchronous sigma-delta modulator is the right implementation for ideal duty-cycle modulation as defined by (1-1). However, the analysis so far is only valid for a static input signal.…”

“…It is clear that as long as (5)(6)(7)(8)(9)(10) Equation (5-9a) can be represented by (5)(6)(7)(8)(9)(10)(11) After insertion of (5-11) into (5-5) we find for the frequencydetermining equation (5)(6)(7)(8)(9)(10)(11)(12) If the loop filter has a 6 dB/octave roll off at frequencies , (5)(6)(7)(8)(9)(10)(11)(12) can be evaluated as before to (5)(6)(7)(8)(9)(10)(11)(12)(13) The center frequency depends on the transfer characteristic of the loop filter. By generally modeling the loop filter by a second-order transfer characteristic with a double pole and a zero (5)(6)(7)(8)(9)(10)(11)(12)(13)(14) and choosing and , it follows from (5-12) that (5)<...>…”

“…By generally modeling the loop filter by a second-order transfer characteristic with a double pole and a zero (5)(6)(7)(8)(9)(10)(11)(12)(13)(14) and choosing and , it follows from (5-12) that (5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15) The conclusion is that an asynchronous sigma-delta modulator approximately implements an ideal duty cycle scheme. The higher the outband suppression over the passband, the better the approximation.…”

“…It is shown in Appendix II that (5-9) can be evaluated to (5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16) where and (5-17)…”