No abstract

This paper describes an analogi digital approach to data clock recovery which allows the implementation of a quasi digital PLL with an effective local clock fr equcncy of I GHz in 21lm CMOS. The large phase jumps normally associated with digital PLLs are avoided' .The basic concept of the clock recovery system is sho wn in Figure 1. A long ring oscillator (32 stages in this example) is per manently frequency-locked to a reference frequency at the data window rate, (the read clock in the case of a disk drive data sep arator). Since thc dynamics of this loop do not affect phase acquisilion or tracking, the design is non-critical. Each tap on the ring oscillator is used tD latch data samples into one of the 32 latches, so that at the end of one round trip (one bit lime) 32 sa mples spaced 1 gate delay apart are stored in the 32 data latches. In 21lm technulogy this gives an effective "mplr rate of IGHz. In 11lm it i. ab out JGllz. After SUbsequently being moved to a separate holding regis ter, the bit pattern is evaluated to determine the location of valid transitions in the data window using digital transition detectors of complexity appropriate to the application. Noise filtering is easily applied to eliminate the effects of isolated noise pulses and metastahility.PLL operation is purely digital and is based on the locatiun of detected transitiuns. The center of the curren t winduw is held in a current-phase tap register, and this register is updated by the digitally lowpass filtered phase error signal. The phase error signal is simply the difference in tap location bet ween th e current window center and the occurrence of a valid data transi tion. Zero phase start, variable loop lime constant, and other modes are implemented digitally. Other speciali7.ed disk drive function s, such as variable win do" width and offset, and pul se pail' ing compensation, can also be implemented directly in the digital domain.The most critical circuit issue in this approach to high-speed clock recovery is phase noise in the data-sampling process, whieh arises from a number of sources including ring oscillator phase noise due to the inherent thermal noise in the inverters them selves, noise due to power supply noise injection, and metasta bil ity in the lalehes med to sample the data.The first-order analysis of thermal noise accumulation in dicates that it is related to the thermal noise at the input of each inverter stage, inverter rise time, signal swing, and loop band.width. For a given technology and set of design parameters, the total effective mean-square thermal noise at the input of each in verter, when the inverter is in its active region, is related to v'kT le gs where C g a is the gate capacitance of the invert er stage. A sampling jilt�r of .07ns rms dictat�d the use of large devices (160/2) in the inverter chain from kT Ie noise considerations.A second major issue is coupling of supply noise. Tradi tionally, CMOS ring-oscillator-based PLLs have used starved in verters together with, for example, an on-chip regulator to ...

Capacitively transduced micromechanical disk resonators that exhibit simultaneous low motional resistance (< 130 Ω) and high Q (>70,000) at 61 MHz are demonstrated using an improved ALDpartial electrode-to-resonator gap filling technique that reduces the Q-limiting surface losses of previous renditions by adding an alumina pre-coating before ALD of the gap-filling high-k dielectric. This work increases the Q over the ~10,000 of previous renditions by more than 6× towards demonstration of the first VHF micromechanical resonators in any material, piezoelectric or not, to meet the simultaneous high Q (>50,000) and low motional resistance R x (< 200Ω) specs highly desired for front-end frequency channelizer requirements in cognitive and software-defined radio architectures. This work finally overcomes the high impedance bottleneck that has plagued capacitively transduced micromechanical resonators over the past decade.

Micromechanical resonant displacement gain stages have been demonstrated that employ directionally engineered stiffnesses in resonant structures to effect displacement amplification from a driven input axis to an output axis. Specifically, the introduction of slots along the output axis of a 53-MHz wine-glass mode disk resonator structure realizes a single gain stage with a measured input-to-output displacement amplification of 3.08x. Multiple such mechanical displacement gain stages can then be cascaded in series via half-wavelength beam couplers to achieve multiplicative gain factors; e.g., two cascaded gain stages achieve a total measured gain of 7.94x. The devices have also been operated as resonant switches, where displacement gain allows impact switching via actuation voltages of only 400mV, which is 6x smaller than for previous resoswitches without displacement gain. The availability of such high frequency displacement gain strategies for resonant switches may soon allow purely mechanical periodic switching applications (such as power amplifiers and power converters) with much higher efficiencies than current transistor-based versions.

No abstract