A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS

Kim, B.; Helman, David; Gray, P.R.

doi:10.1109/4.62166

Cited by 108 publications

(19 citation statements)

References 4 publications

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“…The full swing ring VCO is not suitable to be used in wireless capsule endoscope system for its high dynamic power consumption. So in this design, the fixed swing ring VCO using the replica bias technique is explored [16]. This VCO includes three delay stages and each delay cell is realized by the source-coupled circuit with PMOS differential input devices and NMOS triode-region load devices.…”

Section: Low-frequency Phase-locked Loop (Pll)mentioning

confidence: 99%

WBAN Transceiver Design

Wang

Jiang

Chen

2013

CMOS IC Design for Wireless Medical and Health Care

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The tremendous progress in wireless medical and health care applications in recent years, as well as the significant improvements in wireless communication and semiconductor technologies, led to the rapid development in the wireless body area networks (WBAN) technologies [1,2], which can be used to connected the PBS and SIDs in the wireless medical/health care systems as shown in Chap. 2. Frequency Bands for WBAN TransceiversThe IEEE 802.15.6 WBAN standard was released by the IEEE LAN/MAN standards committee for the short-range low-power WBAN operated on, in, or around the human body (but not limited to humans) in February, 2012 [3]. The standard physical (PHY) layer defines a narrow band (NB) mode compliant device (hub/node, corresponding to PBS/SID in the application systems) shall be able to support at least one of the following frequency bands: 402-405, 420-450, 863-870, 902-928, 950-958, 2,360-2,400, and 2,400-2,483.5 MHz. Before the 802.15.6 standard was released, IEEE 802.15.4/ZigBee low-rate wireless personal area network (LR-WPAN) standard was also widely used for WBAN devices [4]. The IEEE 802.15.4 standard PHY layer defines its operation on one of the three possible unlicensed frequency bands: 868, 902-928, and 2,400-2,483.5 MHz [5]. In some occasions, the below VHF band is used for WBAN, including 6.78 MHz, 13.56 MHz, 27.15 MHz, and 9-315 kHz for inductive link.The frequency available for WBAN in 400 MHz UHF, 2.4 GHz ISM and UWB bands for different countries and areas are illustrated in Fig. 4.1 [6].Note that in real applications, only the 400 MHz and 2.4 GHz bands are most commonly used for the wireless medical and health care applications, since the 400 MHz band signal has small through-body transmission loss, and the There are three types of wireless communications in WBAN as mentioned below:1. In the body: SID inside human body, PBS outside body 2. On the body: SID and PBS attached to the body 3. Around the body: SID attached to body, PBS near the body Whether to use the 400 MHz band or the 2.4 GHz band depends on the real application conditions. To satisfy the miniaturization and low energy consumption requirements of the different WBAN applications, in-body and on/around-body SIDs (nodes) usually work on different communication frequencies. High frequency helps to reduce the antenna size, and the on/around-body nodes are usually designed in 2.4 GHz band to make their dimensions acceptable. However, the 2.4 GHz electromagnetic wave shows more propagation attenuation through the body tissue than the 400 MHz wave. In some applications, it is a good choice to choose 400 MHz band for in-body nodes to minimize the power consumption. Thanks to the high relative permittivity of the body tissue, which is about 30~60 in different tissues. The antenna of in-body nodes still can be designed in small dimensions. The comparison of the 400 MHz band and the 2.4 GHz band is shown in Table 4.1. Previously reported wireless transceivers for WBAN PBS (hubs) only focused on the 400 MHz or the 2.4 GHz single band op...

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Section: Low-frequency Phase-locked Loop (Pll)mentioning

confidence: 99%

WBAN Transceiver Design

Wang

Jiang

Chen

2013

CMOS IC Design for Wireless Medical and Health Care

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“…A Voltage controlled oscillator is an electronic oscillator whose oscillation frequency is directly related to the voltage at its input. The applied input voltage determines the instantaneous oscillation frequency [3]. The VCO produces a signal which is send through the phase detector where the phase is been compared with the reference signal hence a difference or error voltage is produced, resulting to the phase difference between the two signals…”

Section: Voltage Controlled Oscillatormentioning

confidence: 99%

Optimization of VLSI Architecture for High Performance PLL

Baluprithviraj¹

2017

IJRASET

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PLL itself is a mixed signal circuit which has design challenge at high frequencies. The phase locked loop is designed using VLSI technology, which in turn offers high speed performance at low power. In this paper, the faster locking of the PLL is mainly concentrated by properly choosing the circuit architecture and parameters. The optimization of the VCO circuit is carried out to get a better frequency precision. The work characterizes the layout design of Phased Lock Loop PLL with multiple outputs. Effort has been made to design and implement using low power sub threshold D flip flop. The design implemented in analog design tool from Microwind 3.1 where each sub block is designed at its low power design.

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“…New sampling circuit techniques have been proposed to improve resolution by controlling the sampling time interval. This has been done trough the introduction of a controlled delay in the data path (Kim, 1990) or in the clock path (Bazers, 1992). It is shown that a better resolution can be obtained by means of introduction of simultaneous delays in both paths, data and clock, as illustrated in Figure 1 (Gray, 1994).…”

Section: Introductionmentioning

confidence: 99%

A 3.3 Gb/s Sample Circuit with GaAs MESFET Technology and SCFL Gates

Marco

Noije²,

Swart

1997

VLSI: Integrated Systems on Silicon

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This paper presents the implementation of the sampling technique by means of the coordinated delays' method, using the SCFL (Source Coupled FET Logic) logic in GaAs MESFET technology. This technique presents a high resolution and is based on controlling delays in the clock and in the data signal paths, by means of delay elements. The resolution is related to the difference in the delay in both paths. The delay elements are implemented by means of differential invertors, in SCFL logic. A sample circuit of 64 stages has been designed. Its operation has been simulated using the HSPICE program that resulted in a high resolution at a bit rate of 3.33 Gb/s. The circuit prototypes are being fabricated at Vitesse Semiconductor, using the H-GaAs III process with 0.6Jlm gate length. Measurement results "like maximum rate, resolution and jitter" will be presented at the meeting.

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A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS

Cited by 108 publications

References 4 publications

WBAN Transceiver Design

WBAN Transceiver Design

Optimization of VLSI Architecture for High Performance PLL

A 3.3 Gb/s Sample Circuit with GaAs MESFET Technology and SCFL Gates

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