A 300 MHz quadrature direct digital synthesizer/mixer in 0.25 μm CMOS

Abstract

The frequency synthesis and mixing operation of Equation (1) accepts an input sequence with x-y coordinates [X I (n), Y I (n)] and an input frequency control word f, producing the output sequence [X O (n), Y O (n)].(1)The common implementation of (1) employs a DDFS to generate sin(2πnf) and cos(2πnf), feeding a complex multiplier (mixer) (Figure 7.5.1). Most DDFS architectures use lookup tables with pre-computed stored sine and cosine values. The exponential dependence between table size and phase word-length is a severe drawback for such implementations. This IC, based on the Figure 7.5.2 architecture, treats Equation (1) from the perspective of rotating a point (X I , Y I ) in the x-y plane around the origin by an angle θ = 2πnf, to reach (X O , Y O ). The overall rotation uses two stages, coarse and fine, along with accurate small-angle approximations for sine and cosine. These approximations eliminate the need for a large lookup table [2]. In Figure 7.5.2, the phase accumulator and W-bit normalized rotation angle θ = are standard DDFS components, as is the partitioning of θ's three MSBs to reduce the rotation angle to φ in the interval [0, ]. This is accomplished by conditionally interchanging the input coordinates (X I , Y I ), and re-creating the correct output point (X O , Y O ) via conditional interchange and negation operations. With an N-fractional-bit output precision, the partitioning of φ = φ M + φ L , where φ M denotes the +1 MSBs, allows Equation (1) to be implemented in two stages, the first rotating (X I , Y I ) by φ M to reach a point (X T , Y T ) and the second rotating (X T , Y T ) by φ L to obtain (X O , Y O ). Since φ L <2 -, the approximations sin φ L ≈ φ L and cos φ L ≈1-φ L eliminate the need to store sine and cosine values for φ L . For this IC, N = 11 and W = 15; hence φ has 13 bits. φ M requires +1=5b and the remaining 8 bits constitute φ L . The coarse lookup table size is 2 +1. Eliminating the lookup for φ L reduces overall table size from 2 12 + 1 = 4097 locations to 2 4 + 1 = 17 locations, a reduction factor of =241. The output error due to the approximations does not affect the 13b output data [2]. With W = 15 the worst-case spur is 90.3dBc [3].Sinθ 1 is defined by rounding sin φ M up to +1 fractional bits and cosθ 1 by truncating cosθ 1 to fractional bits. Using sinθ 1 and cosθ 1 in the coarse stage significantly reduces the number of partial products in multipliers #1 -#4. Compensation for these modifications is by adjusting the rotation angle and correcting the magnitude in the fine stage. The new coarse rotation angle is θ m =arctan . The fine stage rotation therefore becomes θ 1 = φ−θ m = φ L + φ m -θ m , which is obtained by storing φ m -θ m in the coarse lookup table and adding it to φ L . The fine stage magnitude adjustment introduces in Figure 7.5.2. The inputs of multipliers #5 -#9 are appropriately truncated to reduce the partial products while maintaining the desired output error bound. Figure 7.5.2 reflects these reductions.The following important points should be not...

A two-stage angle-rotation architecture and its error analysis for efficient digital mixer implementation

“…It is shown that, given an overall output precision requirement, the size of all arithmetic components can be accurately determined to satisfy such a requirement while using minimal hardware. The theory, architecture and error analysis developed here support recently reported integrated circuit implementations [6]- [8]. Other two-stage DDS/mixer implementations, also employing small ROMs along with computational circuitry, have recently appeared [9], [10].…”

“…Simulations and, more recently, the design, fabrication and testing of an integrated circuit prototype [6], [7] (and [8] for a one-output system), have verified that in comparison to one of the best prior implementations of a single-stage digital mixer [1], optimized for a 14-bit input angle, the two-stage method presented here achieves a 6-dB better SFDR while using a comparable amount of circuitry. In addition, since the two-stage structure employs only a small ROM, it overcomes the problem of slow access time that can occur when large ROMs are used, thereby facilitating a higher data rate.…”

Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

“…In order to exactly rotate by , a full-precision complex multiplier is needed. However, the coarse rotation does not need to be exact, because the coarse rotation error, if it exists, can be corrected by the fine rotation [7]. Fig.…”

“…In order to reduce the spurious tones, a significant number of iterations and high resolution of the datapath are required. Using a computational algorithm and a lookup table in a combined approach can offer better optimization in hardware complexity and speed [6], [7]. Further reduction of the lookup table size is desired as the implementation cost of a digital communication system becomes more important.…”

Design of direct digital frequency synthesizers based on unilateral second-order approximations

“…The most critical stage in a DDFS is the PSAC. Many prior works for improving the performance of PSAC include angular decomposition techniques [1,[3][4][5][6], angle rotation methods [7][8][9], polynomial approximations [10][11][12], and sine amplitude compression methods [13][14][15][16]. In the sine amplitude compression methods, they only use linear approximations to decrease a ROM size.…”