A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

Kim, Junseok; Seo, Young-Hun; Suh, Yunjae; Park, Hong-June; Sim, Jae‐Yoon

doi:10.1109/jssc.2012.2217892

Cited by 53 publications

(20 citation statements)

References 17 publications

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“…The voltage residue of stage 1 is ¡120 mV. Moreover, the voltage residues of the stages 2 and 3 are ¡211 and ¡209 mV, respectively and are proved by (3)(4)(5)(6)(7). Figure 13 shows comparator 2 waveforms of the three stages of pipeline operation in the proposed TDC.…”

Section: Simulation Resultsmentioning

confidence: 85%

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Design of a Novel Pipeline Time-to-Digital Converter Based on Dual-Slope Interpolation and Time Amplification

Rezvanyvardom

Farshidi

2015

IETE Journal of Research

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In this paper, a novel pipeline time-to-digital converter (TDC) is presented which employs dual-slope analog interpolation and time amplification techniques for digitizing the time interval between two input signals. The proposed converter will be a 9-bit pipeline TDC which contains three 2.5 b/stage TDCs based on analog interpolation and a delay line TDC stage. The proposed converter features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations, and high accuracy compared with the TDCs that have previously been proposed. This converter improves the resolution and the dynamic range. Also, the converter reduces the active chip area, the power consumption, and the figure of merit. In addition, the integral nonlinearity and differential nonlinearity errors are improved. In order to evaluate the idea, the proposed TDC is designed in TSMC 0.18mm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

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Section: Simulation Resultsmentioning

confidence: 85%

“…The simulated TDC achieves an input dynamic range (DR) of 300 ps and a time resolution of (2t q =ð4£4£4£4Þ D 0:195 ps ). Also, the total power consumption of the pipelined TDC is 720 mW which shows an improvement in comparison with the previous pipelined TDC [8,13].…”

Section: Simulation Resultsmentioning

confidence: 87%

Design of a Novel Pipeline Time-to-Digital Converter Based on Dual-Slope Interpolation and Time Amplification

Rezvanyvardom

Farshidi

2015

IETE Journal of Research

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“…According to (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15), the input signals of stages 2-4 are calculated as:…”

Section: E®ect Of a Mismatch Error On The Performance Of The Convertermentioning

confidence: 99%

“…4 Analog interpolation TDCs have high precision and time resolution. Another possible methodology for TDC to sustain¯ne resolution and good linearity is to utilize pipeline and time ampli¯cation structure 11,12 which is a two-step TDC that ampli¯es the time residue after a coarse conversion and subsequently performs a¯ne conversion. This paper presents a novel approach for pipeline TDCs.…”

Section: Introductionmentioning

confidence: 99%

A New Triple-Slope Pipelined Time to Digital Converter by Stretching of Time

Rezvanyvardom

Farshidi

2015

J CIRCUIT SYST COMP

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This study investigates a novel approach for pipeline time-to-digital converters (TDCs) which employs analog interpolation and time stretching techniques for digitizing the time interval between two input signals as well as increasing resolution. In the proposed converter, analog interpolation is performed based on a triple-slope conversion. This converter will be a 9-bit pipeline TDC which contains three time stretching ampli¯ers (TSAs) and four 2.5-b/stage TDCs. This converter does not use delay lines in its structure. It features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations and high accuracy compared with the TDCs which have previously been proposed. Also, the time resolution, the dynamic range and the linear range of the TDC are improved. The proposed structure reduces the active chip area, the power consumption and the¯gure of merit (FoM). In addition, the integral nonlinearity (INL) and the di®erential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the TDC is designed in TSMC 45-nm CMOS technology and simulated. Comparison of the theoretical and simulation results con¯rms the bene¯ts of the proposed TDC.

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“…Moreover, the recent rapid development of solid-state, multi-pixel photo-sensors for PET detectors has posed further challenges for the design of monolithic, multi-channel TDCs, because investigations of readout schemes for this new type of detector rely predominantly on time readout techniques [2]. Because application-specific integrated circuits (ASICs) offer considerable design flexibility and minimal delays, ASIC-based TDCs can deliver high resolution and precision of down to a few picoseconds [3]. Although such "off-the-shelf" TDCs can be employed in PET systems, the necessity of using a custom data acquisition system (DAQ) makes TDCs implemented on Field Programmable Gate Arrays (FPGAs) desirable.…”

Section: Introductionmentioning

confidence: 99%

A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA

Liu

Wang

2015

IEEE Trans. Nucl. Sci.

104

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Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device.Index Terms-Bin realignment, Field programmable gate array (FPGA), measurement throughput, multi-channel time-to-digital converter (TDC), RMS resolution, thermometer-to-binary encoder, time-to-digital converter.

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A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

Cited by 53 publications

References 17 publications

Design of a Novel Pipeline Time-to-Digital Converter Based on Dual-Slope Interpolation and Time Amplification

Design of a Novel Pipeline Time-to-Digital Converter Based on Dual-Slope Interpolation and Time Amplification

A New Triple-Slope Pipelined Time to Digital Converter by Stretching of Time

A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA

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