A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages

Leuschner, Stephan; Pinarello, Sandro; Hodel, U.; Mueller, Jan-Erik; Klär, H.

doi:10.1109/rfic.2010.5477401

Cited by 23 publications

(4 citation statements)

References 4 publications

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“…Theoretically, the maximum efficiency of Class A, AB, B and C PAs are 50%, 50%-78% (0-6 dB gain drop), 78.5% (6 dB gain drop) and 78.5% (greater than 6 dB gain drop), respectively. Studies [13][14][15][16][17] have shown some common techniques to improve the efficiency of CMOS PAs. Either, for a 20 MHz narrowband at2.4 GHz, or 10 MHz narrowband at sub-1 GHz, it is still a challenge for circuit designers to boost PAE of PA, especially when avoiding balun networks and high inductances models.…”

Section: Commonly Used Techniques In Traditional Pa Architecturesmentioning

confidence: 99%

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Akhter

Amin

Zia

2022

IET Circuits, Devices & Syst

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This article presents the design and optimisation of a sub‐1 GHz class‐F ultra‐low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class‐F PA. The ET consist of a pre‐amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class‐F with gate‐to‐drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long‐range low power wireless local area network IEEE 802.11ah standard. The inductor‐less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

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Section: Commonly Used Techniques In Traditional Pa Architecturesmentioning

confidence: 99%

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Akhter

Amin

Zia

2022

IET Circuits, Devices & Syst

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“…7. A successful implementation of this approach is discussed in Leuschner et al (2010) and Leuschner et al (2011). The baseband impedance Z BB is seen from the cascade load transistor into V DD nodes.…”

Section: Dynamic Gate Modulation (Concept Of Vg2 Modulation)mentioning

confidence: 99%

Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation

et al. 2017

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Abstract. This paper reports on an effective root-cause analysis method of memory effects in power amplifiers, as well as introduces compensation techniques on a circuit design level. Despite conventional memory-effect approaches, the discussed method uses a two-tone scan over a wide operation and modulation range. This enables an in-depth study of physical causes and helps to implement compensation techniques at design stage. On the one hand, this circuit investigation is optimized using an automated SystemC model parametrized with real device and measurement values. Hence, computation time is widely reduced which shortens design cycles. On the other hand, the implementation of the derived circuit compensation means will reduce the complexity of digital pre-distortion due to a reduced memory-effect induced AM/AM and AM/PM hysteresis. The approach is demonstrated on a 65 nm CMOS power amplifier with an OIP1 of 27 dBm and a PAE of over 30 % using WCDMA and LTE signals. In fact, mismatch could be reduced by more than 8 %.

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“…The first one has been described elsewhere [14] and is illustrated in Figure 5.21. Unfortunately, there is a limitation because of the biasing of the P-substrate.…”

Section: Intrinsically Robust Designmentioning

confidence: 99%

Reliable Power Amplifier

Martineau

2015

Linearization and Efficiency Enhancement Techniques for Silicon Power Amplifiers

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A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages

Cited by 23 publications

References 4 publications

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation

Reliable Power Amplifier

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