A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS

Chan, Kok Lim; Tan, Kee Hian; Frans, Yohan; Im, Jungho; Upadhyaya, Parag; Lim, Siok Wei; Roldan, Arianne; Narang, Nakul; Koay, Chin Yang; Zhao, Hongyuan; Chiang, Po-Jui; Chang, Ken

doi:10.1109/jssc.2017.2714180

Cited by 29 publications

(10 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

“…The last example is the output driver for high-speed I/O link. On the right side of Figure 12, we can find a conceptual diagram of a source-series terminated (SST) driver, which is also known as a voltage-mode driver [35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50]. Instead of relying on a parallel resistance to match the driver's output impedance with the characteristic impedance of the transmission channel, the SST driver adopts series termination.…”

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

“…To resolve this issue, a series resistance is placed at the output of the SST driver, as shown in Figure 13 [37,[46][47][48]. The turn-on resistance of the transistor is reduced here (i.e., 25 Ω) to make the To resolve this issue, a series resistance is placed at the output of the SST driver, as shown in Figure 13 [37,[46][47][48]. The turn-on resistance of the transistor is reduced here (i.e., 25 Ω) to make the sum with the series resistance be 50 Ω.…”

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

See 2 more Smart Citations

CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

View full text Add to dashboard Cite

Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

show abstract

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

See 1 more Smart Citation

CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

View full text Add to dashboard Cite

show abstract

“…2.4 The impedance calibration scheme Fig. 5 shows that the impedance calibration scheme is a novel method based on an analog technique [28,29]. Unlike conventional impedance calibration technique using a digital method [30,31], the proposed impedance calibration scheme achieves the impedance calibration with higher precision of calibration.…”

Section: Output Drivermentioning

confidence: 99%

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Bai

Zhao

Zuo

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

This study presents an 8 Gbps low-power source-series terminated (SST) transmitter for high-speed serial links. The proposed transmitter consists of a novel hybrid 20:2 multiplexer followed by a three-tap feed-forward equalizer (FFE) and a shunt path SST driver. In addition, a high-precision impedance calibration circuit with slice unit replication is proposed to match the characteristic impedance of channel, whose maximum calibration error is 0.002%. Fabricated in 55-nm CMOS technology and has area of 0.024 mm 2 . Measurement results show that the transmitter achieves data rate of 8 Gbps while maintaining good performance. The transmitter has output swing of 510 mV with −6 dB post-tap equalization, and it consumes 15.1 mW under 1.2 V power supply.

show abstract

“…In addition, this type of driver has worse energy efficiency than a voltage-mode driver. Implementing the FFE in the voltagemode driver can alleviate these issues [9]- [12]. However, in the voltage-mode driver, the output driver segmentation used to implement the equalization limits the FFE resolution, causes routing congestion, and increases the pre-driver complexity [13].…”

Section: Introductionmentioning

confidence: 99%

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

2022

View full text Add to dashboard Cite

Herein, the analog-based, 2-tap feed-forward equalization (FFE) voltage-mode transmitter using dual supply/ground voltage regulation is presented. In an FFE data modulator, the data are divided into transition and non-transition segments, and are transmitted to the main-and post-tap drivers. By using dual voltage regulation, flexible FFE strength adjustment is possible without process dependency, and the shortcurrent path is eliminated, thus improving the overall energy efficiency. Furthermore, this structure with independent impedance calibration loops has good on-resistance and return loss characteristics, thereby securing signal integrity. In addition, by regulating the supply/ground voltages, the output swing and common-mode voltage can be adjusted independently. Therefore, our transmitter can serve multiple standards and channel environments with a single design. To verify the effectiveness of our method, we designed a prototype of the source-synchronous transmitter in a 65 nm CMOS process, and its performance was compared with that of a conventional FFE design. The simulation results show that the proposed design has better on-resistance, return loss, and FFE controllability, and it has an energy efficiency of 2.23 pJ/bit at 20 Gb/s.

show abstract

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS

Cited by 29 publications

References 8 publications

CMOS Inverter as Analog Circuit: An Overview

CMOS Inverter as Analog Circuit: An Overview

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters

Contact Info

Product

Resources

About