A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

Lee, Jun Gyu; Masui, Shoichi

doi:10.1587/elex.9.477

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…Due to the low complexity in the design, the power consumption will be significantly lower. The binary frequency searching method is used to lock as shown in Lee et al (2012). To realise this implementation method a finite state machine (FSM) will be used.…”

Section: Experimental Results and Performance Comparisonmentioning

confidence: 99%

“…During the period of open-loop, capacitors used in VCO are tuned to accommodate to each band of operation, and subsequently, the PLL loop is closed for the frequency synthesis (Shin and Shin, 2010). And from the implementation, the inaccurate PLL approaches such as a periodical calibrates digitally controlled oscillator (DCO) (Lee et al, 2012) or a PLL operated in burst mode, named as duty-cycled PLL (Drago et al, 2010) cannot be utilised from the stringent frequency resolution and phase noise performance.…”

Section: Division Controlmentioning

confidence: 99%

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Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator

Anushkannan¹,

Mangalam

2020

IJAIP

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This paper proposes a new area-efficient, low-power and low-jitter phased-locked loop (PLL) architecture working off a low frequency reference. In this paper, new PLL is proposed with a new locking procedure with low complexity which results in ultra low power design. The main challenge to design the proposed PLL is to keep the area small while meeting the required low jitter. The proposed method was designed using only two up-down counters for finding the reference frequency. An efficient glitch removal filter and new low power DCO also introduced in this paper. The proposed DCO achieves a reasonably high resolution of 1ps. The PLL architecture was demonstrated for different frequency ranges from 100-400 MHz. The power consumption of proposed PLL at 500 MHz frequency is 820 µW. The proposed PLL is simulated in 180 nm with Tanner EDA and verified.

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Section: Experimental Results and Performance Comparisonmentioning

confidence: 99%

Section: Division Controlmentioning

confidence: 99%

Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator

Anushkannan¹,

Mangalam

2020

IJAIP

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Recent Advances in Graphene Homogeneous p–n Junction for Optoelectronics

Tian

Tang

Teng

et al. 2019

Adv Materials Technologies

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Graphene has been widely used as electrodes and active layers in optoelectronics due to its diverse excellent performances, such as high mobility, large thermal conductivity and high specific surface area etc. Methodology for constructing p-n junction has becoming an important consideration in improving the performance of optoelectronic devices and broadening of its application in related fields. Currently, graphene based p-n junction has been explored and different structures have also been investigated. This review paper summaries the recent progress on graphene homogeneous p-n junction, ranging from preparation of front-end materials (e.g. p-and n-type graphene) to building of planar and vertical p-n junctions. Furthermore, p-n junction via electrical modulation is described. The requirements for building the graphene homogeneous p-n junction, and the advantages and drawbacks of the different structures of the p-n junction are also discussed. Finally, a preferential technique to fabricate high performance p-and n-type graphene and building of the p-n junction is evaluated. This paper therefore provides an important indication on the future direction on the application of graphene in optoelectronics. 2 ranging applications, such as logical rectifier circuit [10,11] , field-effect optoelectronic transistor [12-14] , multimode non-volatile memory [15] , rectifier memory [16,17] , optoelectronic storage [18,19] , photovoltaic device [20] , photodetector [21,22] and gas sensor [23,24] etc. Consequently, it is obvious to study new material system for the p-n junction that will enhance the performance of current devices and also lead to the development of new devices. In general, p-n junction can be categorized into heterojunction and homojunction. If same materials are used, the p-n junction is known as homogeneous junction or homojunction. There are many advantages of homogeneous p-n junction, for example, there is no issue on lattice mismatch, which will result in surface defects, since p and n layers are of the same materials. Moreover, the use of the same materials in homogeneous p-n junction leads to uniform energy band gap across the device structure, as shown in Figure 1a. Depletion region is formed at the junction between p and n regions, and the alignment of Fermi level (E f) promotes band bending at the depletion region when the same semiconducting materials are used to construct the p-n junction, as represented in Figure 1b. Such homogeneous p-n junction is of great significance in the field of optoelectronics. Figure 1c illustrates the charge transport mechanism under illumination. Upon radiation of light with certain wavelength (hυ ≧ Eg), electrons jump to conduction band in p, n and depletion regions. These electrons and holes arriving at the depletion region are subsequently swept into n-type and p-type regions respectively via the built-in field. As a result, current is generated and a certain voltage is produced due to the accumulation of charges under open circuit conditions. Furthermore, this lead...

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A −0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology

Kimura

Ochi

2015

2015 15th International Symposium on Communications and Information Technologies (ISCIT)

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In this paper, we design and fabricate a voltage booster circuit, aiming at the realization of a monolithic system LSI that utilize on-chip solar cell to eliminate the need for external voltage supply. Since the voltage that can be obtained from an on-chip solar cell is about −0.5V, we need an efficient voltage booster to obtain voltage around +4.0V if we need to program a non-volatile memory on the same chip. First, it is confirmed by circuit simulation that a 10-stage cross-coupled charge pump circuit using 0.18μm process technology can generate +4.0V from −0.5V input. A ring oscillator using current starved inverters with 2R-1T bias circuit is developed, whose frequency is successfully compensated within ±10% for supply voltage ranging between 0.45V and 0.60V. From measurement of the test chip of proposed circuits using Rohm 0.18μm CMOS process technology, it is confirmed that the voltage booster TEG with 2-stage cross-coupled charge pump circuit generates voltage beyond +0.8V from −0.5V input voltage with about 40% efficiency even at a bright environment of 6.1klux illumination. In addition, it is demonstrated that by implementing an on-chip solar cell, the voltage booster, and a standard-cell-based digital circuit in a single chip, an external piezoelectric diaphragm makes a sound only by the power from on-chip solar cell.

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A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

Cited by 3 publications

References 5 publications

Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator

Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator

Recent Advances in Graphene Homogeneous p–n Junction for Optoelectronics

A −0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology

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