A 32-bit CMOS microprocessor with on-chip cache and TLB

Kadota, Hideki; Miyake, J.; Okabayashi, Ichizo; Maeda, Tadashi; Okamoto, Tatsuo; Nakajima, M.; Kagawa, K.

doi:10.1109/jssc.1987.1052816

Cited by 14 publications

(5 citation statements)

References 4 publications

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“…In order to show the feasibility of the new CAM cell for use in a system, transient performance of the new CAM cell used in a translation lookaside buffer (TLB) [7] has been done. Fig.…”

Section: Performance and Discussionmentioning

confidence: 99%

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A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques

Liu

Kuo

2001

IEEE J. Solid-State Circuits

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This paper reports a novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. With two auxiliary pass transistors to dynamically control the bodies of transistors in the tag-compare portion of CAM cell, this SOI CAM cell has a fast tag-compare capability at a low supply voltage of 0.7 V as verified by the results from the two-dimensional semiconductor device simulation program MEDICI. Index Terms-CMOS, content-addressable memory (CAM), dynamic threshold (DTMOS), low voltage, partially depleted (PD) silicon-on-insulator (SOI), tag cell, VLSI. I. INTRODUCTIONC ONTENT-addressable memory (CAM) has been broadly used in many VLSI system applications such as imaging processing, network communication, and parallel data processing to facilitate operations of fast comparison and validation of patterns [1]. As shown in Fig. 1, a conventional 10T CAM cell [2] is composed of two portions: the SRAM portion (transistors M1-M6) and the tag-compare portion (transistors M7-M10) for performing the XOR operation of the data stored in the SRAM cell with the input data at the digit lines. If a logic-1 is stored at the internal storage node n1, which is different from the logic state of the data on the digit line (DL), then the match line (ML) is pulled down to ground, indicating a miss. Along with the increased complexity of the related VLSI systems, the tag-compare operation of a related large-size CAM circuit has become a bottleneck for high-speed applications. This is especially serious for operations using a low supply voltage. Recently, CMOS dynamic threshold (DTMOS) techniques have been reported for their advantages in low-voltage SOI CMOS VLSI circuits [3]-[5]. In this paper, a low-voltage CAM cell structure with a fast tag-compare capability using partially depleted (PD) SOI CMOS DTMOS techniques is described. In the following sections, the new SOI CAM circuit and its operation are described first, followed by performance evaluation and conclusion.

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“…In order to show the feasibility of the new CAM cell for use in a system, transient performance of the new CAM cell used in a translation lookaside buffer (TLB) [7] has been done. Fig.…”

Section: Performance and Discussionmentioning

confidence: 99%

“…Fig. 5 shows the brief critical path during the read access of TLB [7] using the new CAM cell with PD SOI DTMOS techniques. As shown in the figure, the ML is ANDed with a clock signal CLK2 to generate the word line for driving the corresponding SRAM cell-CLK2 serves to detect the miss/hit signal.…”

Section: Performance and Discussionmentioning

confidence: 99%

A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques

Liu

Kuo

2001

IEEE J. Solid-State Circuits

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“…To solve this issue, we chose to implement the counter LRU algorithm [Kadota et al 1987] and program Chameleon microcode to perform replacement operations. This software-based LRU replacement mechanism will read the LRU state of the hit line and broadcast the outcome back to all PEs in the same column.…”

Section: C-mode: Virtualizing Idle Cores For Cachingmentioning

confidence: 99%

Chameleon

Woo

Fryman

Knies

et al. 2010

ACM Trans. Archit. Code Optim.

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Heterogeneous multicore processors have emerged as an energy-and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These processors typically contain a large number of small, computecentric cores for acceleration while keeping one or two high-performance ILP cores on the die to guarantee single-thread performance. Although a major portion of the transistors are occupied by the acceleration cores, these resources will sit idle when running unparallelized legacy codes or the sequential part of an application. To address this underutilization issue, in this article, we introduce Chameleon, a flexible heterogeneous multicore architecture to virtualize these resources for enhancing memory performance when running sequential programs. The Chameleon architecture can dynamically virtualize the idle acceleration cores into a last-level cache, a data prefetcher, or a hybrid between these two techniques. In addition, Chameleon can operate in an adaptive mode that dynamically configures the acceleration cores between the hybrid mode and the prefetchonly mode by monitoring the effectiveness of the Chameleon cache mode. In our evaluation with SPEC2006 benchmark suite, different levels of performance improvements were achieved in different modes for different applications. In the case of the adaptive mode, Chameleon improves the performance of SPECint06 and SPECfp06 by 31% and 15%, on average. When considering only memory-intensive applications, Chameleon improves the system performance by 50% and 26% for SPECint06 and SPECfp06, respectively.

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“…OMMERCIAL and academic microprocessor architec-C tures are increasingly incorporating caches on the processor chip itself to avoid off-chip latencies [3], [6], [8], [12]. These on-chip caches are currently small, but the trend is toward larger sizes to hide relatively slower off-chip memory speeds; thus, these chips devote an increasing portion of their area to the memory (tags and blocks) of the cache.…”

Section: Introductionmentioning

confidence: 99%

“…For each cache, Sohi reports the average miss ratio of several simulations with different fault patterns. He presents results for the number of faulty blocks ranging from 0% to 50% of the blocks in caches of three sizes (256, lK, and 8K bytes), three associativities (direct-mapped, two-way set-associative, and fully associative) and three block sizes (8,16, and 32 bytes).…”

Section: Introductionmentioning

confidence: 99%

Performance implications of tolerating cache faults

Pour

Hill

1993

IEEE Trans. Comput.

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Abstract-Microprocessors are increasingly incorporating one or more on-chip caches. These caches are occupying a greater share of chip area, and thus may be the locus of manufacturing defects. Some of these defects will cause faults in cache tag or data memory. These faults can be tolerated by disabling the cache blocks that contain them. This approach lets chips with defects be used without requiring on-chip caches to have redundant row or columns or to use error correcting codes. Disabling blocks, however, typically increases a cache's miss ratio. This paper investigates how much cache miss ratios increase when blocks are disabled. It shows how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, develops an efficient approach for calculating the exact distribution of miss ratio increases from all fault patterns, and applies this approach to the ATUM traces [l]. Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size, and is negligible (< 2% per defect) unless a set is completely disabled by faults. The maximum relative increase is also acceptable (5% per fault) if no set is entirely disabled.

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A 32-bit CMOS microprocessor with on-chip cache and TLB

Cited by 14 publications

References 4 publications

A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques

A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques

Chameleon

Performance implications of tolerating cache faults

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