Performance implications of tolerating cache faults

Abstract

Abstract-Microprocessors are increasingly incorporating one or more on-chip caches. These caches are occupying a greater share of chip area, and thus may be the locus of manufacturing defects. Some of these defects will cause faults in cache tag or data memory. These faults can be tolerated by disabling the cache blocks that contain them. This approach lets chips with defects be used without requiring on-chip caches to have redundant row or columns or to use error correcting codes. Disabling blocks, however, typically increases a cache's miss ratio. This paper investigates how much cache miss ratios increase when blocks are disabled. It shows how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, develops an efficient approach for calculating the exact distribution of miss ratio increases from all fault patterns, and applies this approach to the ATUM traces [l]. Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size, and is negligible (< 2% per defect) unless a set is completely disabled by faults. The maximum relative increase is also acceptable (5% per fault) if no set is entirely disabled.

Performance-effective operation below Vcc-min

“…Related research was performed by Pour and Hill [17] to study the performance impact of manufacturing faults in caches using a more analytical approach. Lee et al [14] also explored various fault masking strategies for permanent manufacturing faults in caches.…”

An analytical model for the calculation of the Expected Miss Ratio in faulty caches

“…To produce these maps we have used an algorithm called all-associativity simulation [9], previously used in [19]. This algorithm has a complexity order of O(n 2 ).…”

“…Then, we need to calculate the EMR for every possible number of faults. So far, this problem has been solved by means of random fault-maps [19].…”

“…Sohi [22] studied the performance implications of caches with disabled portions such as blocks and sets using several random fault-maps and trace-driven simulation. Pour and Hill [19] extended Sohi's work with a more accurate methodology by introducing the use of the all-associativity simulation to determine within a single run all possible access patterns for an address trace over a cache. In fact, this study provides an expectation for the miss ratio of faulty caches in a similar way as our model does.…”

“…Previous block disabling-based studies (such as [22], [19], [21], [13], [12], [10], [20], [11]) rely on the use of an arbitrary number (small or large) of random fault-maps. Each random fault-map indicates faulty cache cell locations and determines the disabled faulty cache blocks.…”