It is well known that the eye's optics exhibit temporal instability in the form of microfluctuations in focus; however, almost nothing is known of the temporal properties of the eye's other aberrations. We constructed a real-time Hartmann-Shack (HS) wave-front sensor to measure these dynamics at frequencies as high as 60 Hz. To reduce spatial inhomogeneities in the short-exposure HS images, we used a low-coherence source and a scanning system. HS images were collected on three normal subjects with natural and paralyzed accommodation. Average temporal power spectra were computed for the wave-front rms, the Seidel aberrations, and each of 32 Zernike coefficients. The results indicate the presence of fluctuations in all of the eye's aberration, not just defocus. Fluctuations in higher-order aberrations share similar spectra and bandwidths both within and between subjects, dropping at a rate of approximately 4 dB per octave in temporal frequency. The spectrum shape for higher-order aberrations is generally different from that for microfluctuations of accommodation. The origin of these measured fluctuations is not known, and both corneal/lenticular and retinal causes are considered. Under the assumption that they are purely corneal or lenticular, calculations suggest that a perfect adaptive optics system with a closed-loop bandwidth of 1-2 Hz could correct these aberrations well enough to achieve diffraction-limited imaging over a dilated pupil.

Abstract

In the past years Dynamic Voltage and FrequencyScaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won't be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving microarchitectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed (area) over the power budget, than using DVFS alone for matching a predefined power budget. Furthermore, in a near future DVFS will become DFS because lowering the supply voltage will be too expensive in terms of leakage power. At that point, the use of power-saving microarchitectural techniques will become even more energy efficient.

Abstract. Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime examples are the techniques to resize the instruction queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the memory-level parallelism (MLP) of the application and thus incur disproportional performance degradation. We propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resizing that does not affect the MLP of the program. This information is used to override the resizing enforced by feedback mechanisms when this resizing might reduce MLP. We compare our technique to a previously proposed non-MLPaware management technique and our results show a significant increase in EDP savings for most benchmarks of the SPEC2000 suite.

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