Power-aware control speculation through selective throttling

Aragón, Juan L.; González, José María Faci; González, Antonio

doi:10.1109/hpca.2003.1183528

Cited by 42 publications

(34 citation statements)

References 28 publications

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“…There has been work on reducing the energy consumed in the pipeline due to instruction-level speculation following a branch prediction [2,12]. However, the issues addressed are very different.…”

Section: Related Workmentioning

confidence: 99%

Thread-Level Speculation on a CMP can be energy efficient

Renau

Strauß

Ceze

et al. 2005

Proceedings of the 19th Annual International Conference on Supercomputing

102

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Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject of intense research. However, TLS is suspected of being too energy inefficient to compete against conventional processors. In this paper, we refute this claim. To do so, we first identify the main sources of dynamic energy consumption in TLS. Then, we present simple energy-saving optimizations that cut the energy cost of TLS by over 60% on average with minimal performance impact. The resulting TLS CMP, populated with four 3-issue cores, speeds-up full SPECint 2000 codes by 1.27 on average, while keeping the fraction of the chip's energy consumption due to TLS to only 20%. Compared to a 6-issue superscalar at the same frequency, the TLS CMP is on average faster, while consuming only 85% of its total on-chip power.

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Section: Related Workmentioning

confidence: 99%

Thread-Level Speculation on a CMP can be energy efficient

Renau

Strauß

Ceze

et al. 2005

Proceedings of the 19th Annual International Conference on Supercomputing

102

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“…Others have focused on reducing energy consumption in predictors [Parikh et al 2002;Baniasadi and Moshovos 2002] and branch target buffer [Petrov and Orailoglu 2003;Shim et al 2005]. Confidence prediction and throttling [Aragon et al 2003] has been proposed as a way to control overspeculation to limit energy wasted on misspeculated instructions. Our proposal reduces the energy consumption in the front-end and, at the same time, improves the performance by increasing instruction fetch accuracy.…”

Section: Related Workmentioning

confidence: 99%

Block-aware instruction set architecture

Zmily

Kozyrakis

2006

ACM Trans. Archit. Code Optim.

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Instruction delivery is a critical component for wide-issue, high-frequency processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction-cache misses, multicycle instruction-cache accesses, and target or direction mispredictions for control-flow operations. This paper presents a block-aware instruction set (BLISS) that allows software to assist with front-end challenges. BLISS defines basic block descriptors that are stored separately from the actual instructions in a program. We show that BLISS allows for a decoupled front-end that tolerates instruction-cache latency, facilitates instruction prefetching, and leads to higher prediction accuracy.

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“…Energy is saved by not having to fetch, decode and eventually flush these potential wrong-path instructions. Many heuristics have been developed using branch confidence [2], and instruction flow metrics [4] …”

Section: Related Workmentioning

confidence: 99%

“…Although traditional instruction fetch may be unable to effectively utilize the increased execution bandwidth, the IRF allows us to often exploit the additional bandwidth when needed. This is similar in many ways to front-end throttling [28,4,2], which is a technique that seeks to reduce processor energy requirements by not aggressively fetching highly speculative instructions in regions with low instruction level parallelism (ILP). Whereas pipeline throttling actually limits the number of instructions fetched and decoded in a single cycle, the use of an IRF allows the fetch of instructions to remain constant, while supplying additional instructions to decode in regions of dense packing and high ILP.…”

Section: Introductionmentioning

confidence: 99%

Addressing instruction fetch bottlenecks by using an instruction register file

2007

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The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by packing an application's instructions, resulting in decreased code size, reduced energy consumption and improved execution time primarily due to a smaller footprint in the instruction cache. The nature of the IRF also allows the execution of packed instructions to overlap with instruction fetch, thus providing a means for tolerating increased fetch latencies, like those experienced by encrypted ICs as well as the presence of low-power L0 caches. Although previous research has focused on the direct benefits of instruction packing, this paper explores the use of increased fetch bandwidth provided by packed instructions. Small L0 caches improve energy efficiency but can increase execution time due to frequent cache misses. We show that this penalty can be significantly reduced by overlapping the execution of packed instructions with miss stalls. The IRF can also be used to supply additional instructions to a more aggressive execution engine, effectively reducing dependence on instruction cache bandwidth. This can improve energy efficiency, in addition to providing additional flexibility for evaluating various design tradeoffs in a pipeline with asymmetric instruction bandwidth. Thus, we show that the IRF is a complementary technique, operating as a buffer tolerating fetch bottlenecks, as well as providing additional fetch bandwidth for an aggressive pipeline backend.

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Power-aware control speculation through selective throttling

Abstract: Abstract

Cited by 42 publications

References 28 publications

Thread-Level Speculation on a CMP can be energy efficient

Thread-Level Speculation on a CMP can be energy efficient

Block-aware instruction set architecture

Addressing instruction fetch bottlenecks by using an instruction register file

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