Block-aware instruction set architecture

Abstract

Instruction delivery is a critical component for wide-issue, high-frequency processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction-cache misses, multicycle instruction-cache accesses, and target or direction mispredictions for control-flow operations. This paper presents a block-aware instruction set (BLISS) that allows software to assist with front-end challenges. BLISS defines basic block descriptors that are stored separately from the actual instructions in a program. We show that BLISS allows for a decoupled front-end that tolerates instruction-cache latency, facilitates instruction prefetching, and leads to higher prediction accuracy.

Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures

“…There have been many research achievements on hyperblock-like (block with one or multiple exits) prediction over the last few decades [5], [8], [12]- [15]. Though these achievements were based on different research contexts, all of them tend to modify state-of-the-art binary prediction techniques to satisfy the "1 out of N (N is no less than 2)" prediction.…”