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Abstract-In this paper, we settle some problems that are encountered when modeling and synthesizing complex industrial systems by the supervisory control theory. First, modeling such huge systems with explicit state-transition models typically results in an intractable model. An alternative modeling approach is to use extended finite automata (EFAs), which is an augmentation of ordinary automata with variables. The main advantage of utilizing EFAs for modeling is that more compact models are obtained. The second problem concerns the ease to understand and implement the supervisor. To handle this problem, we represent the supervisor in a modular manner by extending the original EFAs by compact conditional expressions. This will provide a framework for the users where they can both model their system and obtain the supervisor in form of EFAs. In order to be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams (BDDs). All computations that are performed in this framework are based on BDD operations. The framework has been implemented in a supervisory control tool and applied to industrially relevant benchmark problems.Index Terms-Binary decision diagrams (BDDs), extended finite automata (EFA), supervisor representation, supervisory control theory (SCT), symbolic representation.

In the supervisory control theory, a supervisor is generated based on given plant and specification models. The supervisor restricts the plant in order to fulfill the specifications. A problem that is typically encountered in industrial applications is that the resulting supervisor is not easily comprehensible for the users. To tackle this problem, we introduce an efficient method to characterize a supervisor by tractable logic conditions, referred to as guards, generated from the models. The guards express under which conditions an event is allowed to occur to fulfill the specifications. To obtain tractable guard expressions, we reduce them by exploiting the structure of the given models. In order to be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams and all computations are performed on these data structures. The algorithms have been implemented in a supervisory control tool and applied to an industrially relevant example. Note to Practitioners-In today's industry, the control functions are implemented to a great extent manually, which makes it a tedious, error-prone, and time consuming process. supervisory control theory (SCT) provides a powerful framework for automatically producing safe and flexible control functions. SCT is based on state-transition models, however, industrial people are used to other representations. Specifically, the interpretation of a control function represented by a huge and cluttered state-transition model requires the maintenance personnel to have other skills than are common today. As a consequence, SCT is seldom utilized in the industry. This paper aims to facilitate the realization and manipulation of control functions that are generated based on SCT. This is performed by restricting the state-transition models by tractable logic conditions extracted from the generated control function. To be able to handle large systems efficiently, the computations are carried out on implicit representations of the state-transition models.

In supervisory control theory, an issue that often arises in real industrial applications is the huge number of states for the supervisor, which requires a lot of memory. Another problem that is typically encountered for the users of supervisory synthesis tools is lack of information and unreadability of the supervisor. In this paper, we introduce a method to characterize a controllable and non-blocking supervisor directly on the modular automata (sub-plants and sub-specifications), by extracting some guard conditions from the synthesized supervisor and the synchronized automaton. Thus, the presented approach may potentially model a complex supervisor using a compact representation whilst not infringe the original modular structure. Furthermore, the guard conditions, which are generated from a set of states, may give the user of the synthesis procedure a better understanding of which states that were removed during the synthesis. In order to obtain more compact guard expressions, we include some unnecessary states (unreachable and extended forbidden states) in the set of states that will be used for guard generation. By exploiting this extra information, it is possible to reduce the logical expressions to more compact guard conditions.

Abstract-Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the faulttolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone.