Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies[Note 1]

Fazeli, Mahdi; Miremadi, Seyed Ghassem; Ejlali, Alireza; Patooghy, Ahmad

doi:10.1049/iet-cdt.2008.0099

Cited by 118 publications

(79 citation statements)

References 29 publications

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“…When an energetic particle striking a gate or a chip may affect multiple sensitive nodes in a circuit through charge sharing and produces bit flip at each node. Therefore single event produces multiple effects this phenomenon is called SEME and it causes a multiple bit flips in the memory cell is called single event multiple upset (SEMU) [8]- [10]. As CMOS emerges into nanoscale technology SEMEs and SEMU are the main effects of energetic particle strikes due to radiation issues [11].…”

Section: Introductionmentioning

confidence: 99%

A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology

Kumar¹,

Padmini²

2016

IJCA

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As CMOS technology down sized into double digit nanometer ranges, variations are a serious concern due to uncertainty in devices and interconnect characteristics. The single event upset (SEU) is changing the state of a memory cell due to the strike of an energetic particle. The single event multiple effects are likely to increase in nanometer CMOS technology due to reduced device size and scaling of power supply voltage.SRAM cells are sensitive to radiation induced hazards. Therefore, designing a reliable novel SRAM cell is an important challenge against SEU. In this paper, the proposed SRAM cell that provides a better features than their recent proposed SRAM cells. The simulation results and analysis represent that the proposed SRAM cell exhibits the high robustness against single event multiple effects (SEMEs). Moreover, the proposed SRAM cell successfully reduced the power consumption by 41% and write delay by 2% in comparison with the existing radiation-hardened SRAM cells at the cost of circuit complexity. The process corner analysis displays the comparison of power and delay of the proposed and existing SRAM cells. It shows that the proposed memory cell consumes less power than previous memory cells.

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Section: Introductionmentioning

confidence: 99%

A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology

Kumar¹,

Padmini²

2016

IJCA

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“…Among sequential elements, latch is the most fragile element to soft error since its latching window is much longer than other register elements [8]. Recently, there are many soft error mitigation latch designs have been proposed [4,5,6,7,8,9]. These designs can be classified into the node strengthen type and the soft-error isolation type.…”

Section: Introductionmentioning

confidence: 99%

“…These designs can be classified into the node strengthen type and the soft-error isolation type. Usually, the soft-error isolation designs [6,7,8,9] can provide more superior soft error resilience by masking the propagation of soft error with a key component, C-element. C-element is supposed to be soft error free.…”

Section: Introductionmentioning

confidence: 99%

Robust C-element design for soft-error mitigation

Wey

Peng

et al. 2015

IEICE Electron. Express

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C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its softerror tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element.

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“…Another effective way to combat soft errors is to use hardened storage circuits, [7] [8] [9] [10] [11]. Although these approaches are more cost-efficient than the traditional TMR-latch [12], they have various drawbacks [7].…”

Section: Introductionmentioning

confidence: 99%

“…Although these approaches are more cost-efficient than the traditional TMR-latch [12], they have various drawbacks [7]. A time redundancy-based, cost-efficient, hardened architecture, Razor, was proposed for timing faults in a DVS system [13].…”

Section: Introductionmentioning

confidence: 99%

SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems

Yang

Zwoliński

2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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Abstract-Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. The result indicates that SETTOFF is suitable for building high reliable systems at lower cost than the traditional techniques.

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Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies[Note 1]

Cited by 118 publications

References 29 publications

A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology

A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology

Robust C-element design for soft-error mitigation

SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems

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