Extraction and representation of a supervisor using guards in extended finite automata

Abstract

In supervisory control theory, an issue that often arises in real industrial applications is the huge number of states for the supervisor, which requires a lot of memory. Another problem that is typically encountered for the users of supervisory synthesis tools is lack of information and unreadability of the supervisor. In this paper, we introduce a method to characterize a controllable and non-blocking supervisor directly on the modular automata (sub-plants and sub-specifications), by extracting some guard conditions from the synthesized supervisor and the synchronized automaton. Thus, the presented approach may potentially model a complex supervisor using a compact representation whilst not infringe the original modular structure. Furthermore, the guard conditions, which are generated from a set of states, may give the user of the synthesis procedure a better understanding of which states that were removed during the synthesis. In order to obtain more compact guard expressions, we include some unnecessary states (unreachable and extended forbidden states) in the set of states that will be used for guard generation. By exploiting this extra information, it is possible to reduce the logical expressions to more compact guard conditions.

A process-theoretic approach to supervisory coordination under partial observation

“…We note that we are developing a supervisory controller synthesis tool as ongoing work, so in order to implement the framework we have to rely on other existing tools, which are not entirely compatible with the theory presented in this paper. We opt for Supremica [26] as a synthesis tool because it provides the greatest modeling convenience and range of options with respect to specifying plants with data and optimized synthesis procedures [17]. We remark that this tool supports only automata-style specifications and CSP-based parallel composition [3,26].…”

“…The control requirements are adapted to fit the input formalism of Supremica, which are finite automata with data variables of an enumerated type [17]. For many practical applications, this formalism has proven to be sufficient, though not entirely flexible and convenient, cf.…”

“…In principle, we allow data elements to be of any type, given by the set D, even though only finite integer and enumerated types are currently supported by the synthesis tool [26], mainly because they support efficient synthesis techniques [17]. By V, we denote the set of data variables, and by F, data expressions involving standard arithmetical operations, also supported by Supremica [26].…”

“…Moreover, this manner of representation of the plant-supervisor communication still prevails in modern state-of-the-art approaches, like [7][8][9][10]. Furthermore, supervisory control loops with state-based [16] and data-based [17] observations, depicted in Fig. 1(c), rely on different forms of synchronization by means of propositional signals [18] or shared variables [19], which should be properly captured.…”

Deadlock avoidance policies for automated manufacturing cells

“…Furthermore, when a transition fires, the associated action functions are applied, updating the corresponding variables. In [34,35], the sought DAP is synthesized in the FSA modeling framework using Binary Decision Diagrams (BDDs) in an effort to alleviate the relevant computational effort, and then it is encoded as guarding conditions in the EFSA.However, the scalability and the size of the thus synthesized DAP are problems that yet need to be addressed for the efficient implementation of this approach.More extensive and comprehensive treatments of many of the results and methodologies that were outlined in the previous paragraphs, can be found in [28,51,54,66]. We conclude our discussion on the key concepts and elements that underlie the current theory on the problem [17] are some of them.…”