A 32-bit microprocessor based on the TRON architecture: Design of the GMicro/100

Shimizu, Toshihisa; Yoshida, Toyohiko; Saito, Yusaku; Matsuo, M.; Enomoto, Tatsuya

doi:10.1109/cmpcon.1988.4823

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…The target machine of the pilot system is the PC9340 [9] workstation. It contains a G M I C R O /~~~ [17] based on the TRON VLSI CPU specification [13], 16M bytes of main memory, lOOM bytes hard disk, and an Ethernet board. Its kernel is based on the ITRON2 specification [14].…”

Section: Pilot Systemmentioning

confidence: 99%

Implementation of label metaphor using shared interaction object architecture

Koshizuka

Satoh²

Proceedings of the 11th TRON Project International Symposium

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Label model is a framework of script processing, which is a natural extension of desktop metaphor like the B T R O N GUI environment. T h e m a i n idea of the label model is that a script program is just a piece of "memo label" attached upon a document, which contains several operations o n the document. In the model, a script program is described as a sequence of operations o n graphical objects of the document data. T h e m a i n contribution of this paper is to demonstrate that shared interaction-object architecture facilitates the implementation of the label model. It is a n architecture model of GUI applications, in which graphical objects of GUI applications are preserved in distributed shared memories specially tailored f o r GUI. This allows script programs to operate the data f r o m outside the GUI applications. T h e major benefit of this architecture is that it satisfies the following two requirements: First, script processing can be handled transparently f r o m GUI applications, second, this architecture gives rather abstract interface of GUI applications to script programs.

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Section: Pilot Systemmentioning

confidence: 99%

Implementation of label metaphor using shared interaction object architecture

Koshizuka

Satoh²

Proceedings of the 11th TRON Project International Symposium

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“…The GMI-CR0/100 is designed as a small personal workstation CPU, an embedded system controller, and a core processor of application specific chips (ASIC's). It has 5-stage instruction pipeline scheme with a branch prediction mechanism and a branch target cache, and achieves two clock cycle execution of simple instructions, such as move, arithmetic and branch instructions [3], [4]. The G M I C R O /~~~ has high-level instructions such as those of bit-map manipulation.…”

Section: Introductionmentioning

confidence: 99%

A 32-bit microprocessor with high performance bit-map manipulation instructions

Shimizu

Iwata

Saito

et al.

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

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The GMICRO/~OO, a 32-bit microprocessor based on the TRON architecture specification, has high performance bit-map manipulation instructions. The bit-map instructions are implemented by pipelining micro-operations and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 t o 3 times faster than repeating move instruction by the software. Microprogram development tools for the G M I C R O /~~~ design are also described in this paper.

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32-bit microprocessors based on the TRON specification

Satoh

Enomoto

1989

Microprocessors and Microsystems

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A 32-bit microprocessor based on the TRON architecture: Design of the GMicro/100

Cited by 8 publications

References 4 publications

Implementation of label metaphor using shared interaction object architecture

Implementation of label metaphor using shared interaction object architecture

A 32-bit microprocessor with high performance bit-map manipulation instructions

32-bit microprocessors based on the TRON specification

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