A 32-bit VLSI digital signal processor

Hayes, W.P.; Kershaw, R. N.; Bays, L.E.; Boddie, J.; Fields, E.M.; Freyman, R.; Garen, C.J.; Hartung, John; Klinikowski, J.; Miller, Carol; Mondal, Kalyan; Moscovitz, H.S.; Rotblum, Y.; Stocker, W.; Tow, J.; Tran, L.V.

doi:10.1109/jssc.1985.1052427

Cited by 34 publications

(7 citation statements)

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“…One is based on monotonic string encoding, the other on a hierarchical counting tree. The monotonic string method [Hayes et al 1985] is typically faster while the counting tree has the advantage in terms of area and energy-efficiency. Because LZA takes leading zero detection (LZD) off the critical path, counting trees are attractive for an approach like Sabrewing.…”

Section: 42mentioning

confidence: 99%

Sabrewing

Bruintjes

Walters

Gerez

et al. 2012

ACM Trans. Archit. Code Optim.

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In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporary processors are practically disjoint. This work presents a new architecture which tightly integrates floating-point and integer arithmetic in a single datapath. It is mainly intended for use in low-power embedded digital signal processors and therefore the following design constraints were important: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology; minimal area and power consumption for applicability in embedded systems. The architecture is tailored to digital signal processing by combining floating-point fused multiply-add and integer multiply-accumulate. It could be deployed in a multi-core system-on-chip designed to support applications with and without dominance of floating-point calculations.The VHDL structural description of this architecture is available for download under BSD license. Besides being configurable at design time, it has been thoroughly checked for IEEE-754 compliance by means of a floating-point test suite originating from the IBM Research Labs. A proof-of-concept has also been implemented using STMicroelectronics 65nm technology. This prototype supports 32-bit signed two's complement integers and 41-bit (8-bit exponent and 32-bit significand) floating-point numbers. Our evaluations show that over 67% energy and 19% area can be saved compared to a reference design in which floating-point and integer arithmetic are implemented separately. The area overhead caused by combining floating-point and integer is less than 5%.Implemented in ST's general-purpose CMOS technology, the design can operate at a frequency of 1.35GHz, while 667MHz can be achieved in low-power CMOS. Considering that the entire datapath is partitioned in just three pipeline stages, and the fact that the design is intended for use in the low-power domain, these frequencies are adequate. They are in fact competitive with current technology low-power floating-point units. Post-layout estimates indicate that the required area of a low-power implementation can be as small as 0.04mm 2 . Power consumption is on the order of several milliwatts. Strengthened by the fact that clock gating could reduce power consumption even further, we think that a shared floating-point and integer architecture is a good choice for signal processing in low-power embedded systems.

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Section: 42mentioning

confidence: 99%

Sabrewing

Bruintjes

Walters

Gerez

et al. 2012

ACM Trans. Archit. Code Optim.

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“…These include the 32bit VLSI chips from AT & T, Phillips and Fujitsu, and the 60MHz DSP chip from Hitachi (Hays et al 1985, Wetten et a / . 1985, Hotta et al 1986, Linderman et a/.…”

Section: Recent Developments In Blmos For High-speed Signal Processorsmentioning

confidence: 99%

Technology compatibility and circuit complementarity of BIMOS

Kal

Chakrabarti

1990

International Journal of Electronics

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“…( [18]. In order to give completeness to this example , a PLA based controller (CTRL) is added, whose outputs are assumed to be fully decoded.…”

Section: Generate Test Schedulesmentioning

confidence: 99%

DFTEXPERT: an expert system for design of testable VLSI circuits

Bhawmik

Chaudhuri

1988

Proceedings of the First International Conference on Industrial and Engineering Applications of Artificial Intelligence and Exp

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To tackle the current day testing complexity of VLSI circuits Design For Testability (DFT) is becoming more of a necessity. However VLSI designers are yet to accept DFT mainly due to lack of effective tools. Expert Systems technology promises to be an useful means to present to the designer the gamut of DFT knowledge developed so far, primarily by test experts, in a more effective way.DFTEXPERT is an attempt towards this direction. This paper presents the major components of DFTEXPERT and also demonstrates its capability through a small illustration.

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A 32-bit VLSI digital signal processor

Cited by 34 publications

References 1 publication

Sabrewing

Sabrewing

Technology compatibility and circuit complementarity of BIMOS

DFTEXPERT: an expert system for design of testable VLSI circuits

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