2011
DOI: 10.1109/jssc.2010.2084450
|View full text |Cite
|
Sign up to set email alerts
|

A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
17
0

Year Published

2011
2011
2017
2017

Publication Types

Select...
4
3
1

Relationship

0
8

Authors

Journals

citations
Cited by 29 publications
(17 citation statements)
references
References 6 publications
0
17
0
Order By: Relevance
“…Other studies also identified charge detrapping as the dominant error source in highly-cycled NAND samples [242]. To overcome this limitation, several solutions have been proposed, including a dummy read [243] or a moving reference [244] scheme and a self-healing approach [245], where a built-in heater in the proximity of the tunnel oxide is used to accelerate damage recovery and prolong the endurance. The insertion of specific block healing cycles during run time was shown to increase lifetime and performance of NAND devices [246], suggesting that distributed healing schemes could be devised to maximize their efficacy while reducing the energy dissipation of such cycles [247].…”
Section: Effect On V T Distribution After Cyclingmentioning
confidence: 99%
“…Other studies also identified charge detrapping as the dominant error source in highly-cycled NAND samples [242]. To overcome this limitation, several solutions have been proposed, including a dummy read [243] or a moving reference [244] scheme and a self-healing approach [245], where a built-in heater in the proximity of the tunnel oxide is used to accelerate damage recovery and prolong the endurance. The insertion of specific block healing cycles during run time was shown to increase lifetime and performance of NAND devices [246], suggesting that distributed healing schemes could be devised to maximize their efficacy while reducing the energy dissipation of such cycles [247].…”
Section: Effect On V T Distribution After Cyclingmentioning
confidence: 99%
“…4) Randomization: In data randomization (or scrambling) of Fig. 9 (a), as well as even distribution of the cells into each programmed level [6], neighboring cell's programmed level should be considered to reduce the interference to victim cell. As shown in Fig.…”
Section: A Electrical Analysis Of Nand Chipsmentioning
confidence: 99%
“…Various operation schemes, such as the modified incremental step pulse program, moving read scheme, virtual negative method and P/E pulse slope control, have been already proposed to improve reliability characteristics [5][6][7]. In this work, the newly adopted operation algorithms such as intelligent incremental step pulse erase (ISPE), various biasing in grouped W/Ls and virtual negative read (VNR) and their results will be exhibited.…”
Section: Introductionmentioning
confidence: 99%
“…As well-known with moving read scheme, this method is wide usage of initial program cell state to adjust and compensate read-bias judging from the amount of left shifted cell distribution. [2]. It's possible to compensate a retention drawback within small Vth window using adjusting read 2 or read 3 sensing level.…”
Section: Moving Read Using Virtual Negative Readmentioning
confidence: 99%
“…According to technology shrink drawback of interference. [2,3] This NAND Flash memory has the average parameter of tPROG is measured in 1361 µs. The performance is calculated in 12.7 MB/s using multi plane and cache program operation in Fig.…”
Section: Performance Enhancementmentioning
confidence: 99%