A High Performance Co-design of 26 nm 64 Gb MLC NAND Flash Memory using the Dedicated NAND Flash Controller

You, Byoung-Sung; Park, Jin-Su; Lee, Sang−Don; Baek, Gwang-Ho; Lee, Jae-Ho; Kim, Minsu; Kim, Jong-Woo; Chung, Hyun Kyu; Jang, Eun-seong; Kim, Taeyoon

doi:10.5573/jsts.2011.11.2.121

Cited by 19 publications

(4 citation statements)

References 5 publications

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“…According to [10], one voltage sensing operation takes approximately 15 μs and 0.81 μJ for a 20 nm-class NAND flash memory device whose page size is 8 KBytes. In order to reduce the number of memory sensing operations while finding the optimal MSRVs, a moving read technique was proposed in [11]. This technique observes the changes in the number of cells that belong to the highest voltage level, i.e.…”

Section: Estimation Of Threshold Voltage Distributionmentioning

confidence: 99%

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Lee

Kim

Sung

2013

SiPS 2013 Proceedings

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The capacity of NAND flash memory has been continuously increased by adopting process technology scaling and multi-level cell (MLC) data coding. However, the reliability of stored data becomes a very important issue because the scaled feature size lowers the number of electrons at each floating-gate while increasing the cell-to-cell interference. In this paper, we review recent advances in signal processing techniques for reliability improvement of sub-20 nm NAND flash memory, which includes estimation of the threshold voltage distribution, cell-to-cell interference cancellation, and optimal multi-level memory sensing. We also present experimental results for the explained signal processing algorithms. Especially, we demonstrate the reliability improvement when combining all these techniques.

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Section: Estimation Of Threshold Voltage Distributionmentioning

confidence: 99%

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Lee

Kim

Sung

2013

SiPS 2013 Proceedings

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“…As NAND flash memory has been scaled down for high density, reliability issues have become critical problems. [1][2][3][4] Reliability issues are usually caused by traps in the oxide layer and at=near the SiO 2 -Si interface. 5) For detailed analysis of main reason affecting those reliability issues, we proposed the method to separate dominant failure mechanisms related to traps [the detrapping mechanism, [6][7][8][9] the trapassisted tunneling mechanism (TAT), [10][11][12][13][14][15] and interface trap recovery mechanism (N it recovery) [16][17][18][19][20][21] ].…”

Section: Introductionmentioning

confidence: 99%

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

Kang¹,

Lee²,

Kwon³

et al. 2015

Jpn. J. Appl. Phys.

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We observed an increase of V th by read disturbance mechanism at programmed threshold voltage state (PV1) and erase state (ERS) states in retention characteristics of sub-20 nm NAND flash main-chip. We also confirmed that the charge gain behavior by read disturbance has dependency on the number of read and cycling operations. As a result, we quantitatively modeled read disturbance mechanism by the amount of final ΔV th and deterioration coefficient α which is related to the number of read operation times. It was also observed that those parameters increase with increasing cycling times and have larger value at ERS state than that at PV1 state.

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“…As NAND Flash memory has been scaled down for high density, reliability issues have become critical problems [1]- [2]. For detailed analysis of main reason affecting retention issues, we proposed the method to separate dominant failure mechanisms related to traps (the detrapping mechanism [3], the trap-assisted tunneling mechanism (TAT) [4] and interface trap recovery mechanism (Nit recovery)) [5].…”

Section: Introductionmentioning

confidence: 99%

Modeling of Read Disturbance Mechanism due to Carrier Trapping in Sub-20nm NAND Flash Memory

Kang¹,

Lee²,

Kwon³

et al. 2014

Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials

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We observed an increase of V th (charge gain) by read disturbance mechanism at PV1 and ERS states in retention characteristics of sub-20nm NAND Flash main-chip. As a result, we quantitatively modeled read disturbance mechanism by the amount of final ΔV th and deterioration coefficient α which is related to the number of read operation times. It was also observed that those parameters increase with increasing cycling times and have larger value at ERS state than that at PV1 state.

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A High Performance Co-design of 26 nm 64 Gb MLC NAND Flash Memory using the Dedicated NAND Flash Controller

Cited by 19 publications

References 5 publications

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

Modeling of Read Disturbance Mechanism due to Carrier Trapping in Sub-20nm NAND Flash Memory

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