A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Tuan, Anh

doi:10.1016/j.sse.2017.10.002

Cited by 9 publications

(7 citation statements)

References 16 publications

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“…Here I cell0 denotes cell read '0' current and I leak0 denotes leakage current for unselected cells storing '0'. Numerous modified read buffers [4], [17]- [27], [29] have been proposed in the literature to deal with the issue encountered in CONV8T cell. These cells include use of either buffer-foot or additional transistors in the read path to minimize the OFF-current thereby improving I ON /I OF F ratio.…”

Section: A Decoupled Read Path 1) Using Single-ended Sensingmentioning

confidence: 99%

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A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Ahmad¹,

Alam²,

Hasan³

et al. 2022

Preprint

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In order to meet the ultra-low power requirement of modern digital systems, voltage scaling is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled technologies significantly affect the stability of an Static Random Access Memory (SRAM) cell. This work provides an extensive review of various designs and techniques for solving issues related to SRAM cell stability. Decoupling the read operation is a commonly used technique for addressing read stability issue. Modified Schmitt-trigger based cell core, loop-cutting and additional discharge path based techniques have also been employed in the literature to enhance the read stability. However, the write-ability and stability of halfselected (HS) cells have been compromised in some of these technique. For write-ability enhancement, most of the techniques involve either weakening of pull-up/pull-down devices (to reduce the current responsible for storing the data) or strengthening of access transistors (to enhance the write current). It includes VDD/VSS -cut off or -floating, feedback cutting, multi-Vth write assist based cells. Apart from discussing the alternative bitcells, we also cover several peripheral read/write assist techniques. WL underdrive (WLUD) and dynamic WLUD are effective read assist techniques. WL -boost, WL -delayed boost, VDD-floating/lowering, transient VDD collapse, VSS raised, dual split control-VSS raised and negative BL (NBL) are among the peripheral techniques for enhancing write-ability. Furthermore, various techniques for mitigating the HS cell issues, such as write-back, column decoupled local wordline, modified bitinterleaving array architecture are discussed. Finally, the Cross-point selection based cell accessing in-built technique is illustrated. Through summary tables, conclusions are also derived for suggesting a circuit of choice for various categories.

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Section: A Decoupled Read Path 1) Using Single-ended Sensingmentioning

confidence: 99%

“…Bitline equalization technique was proposed in [4], [29] to mitigate the data-dependent bitline leakage issue. The read buffer, as shown in Fig.…”

Section: A Decoupled Read Path 1) Using Single-ended Sensingmentioning

confidence: 99%

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Ahmad¹,

Alam²,

Hasan³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Este trabalho selecionou quatro circuitos de SRAM para avaliação, além da célula 6T convencional, todos devidamente ilustrados na Figura 2. Esses circuitos compreendem: A SRAM 8T que possui um mecanismo dedicado que isola os nodos internos durante as operações de leitura [Kim et al 2018]. A SRAM 9T, é baseada na 8T e propõe melhorias para os problemas de corrente de fuga [Kim et al 2018].…”

Section: Metodologiaunclassified

“…Esses circuitos compreendem: A SRAM 8T que possui um mecanismo dedicado que isola os nodos internos durante as operações de leitura [Kim et al 2018]. A SRAM 9T, é baseada na 8T e propõe melhorias para os problemas de corrente de fuga [Kim et al 2018]. A SRAM DICE, uma conhecida topologia de célula robusta que se utiliza de um mecanismo de redundância entre seus nodos internos [Wang et al 2009].…”

Section: Metodologiaunclassified

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Impacto de falhas transientes em memórias SRAM em nanotecnologia

Marques

Meinhardt

Butzen

2020

REIC

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Esse trabalho avalia o impacto de falhas transientes induzidos por radiação em cinco topologias de células SRAM: 6T, 8T, 9T, 8T-SER e DICE. A análise explora as características temporais, de dissipação de potência e o limiar de LET durante a operação de armazenamento. As células de memória foram descritas utilizando o modelo preditivo na tecnologia de 16nm. Os resultados mostram o melhor desempenho da célula DICE como a opção mais robusta quanto aos efeitos de radiação. A célula 8T-SER obteve a melhor estabilidade considerando a tolerância ao ruído. Também são apresentados os ganhos na utilização da célula 8T em relação a 6T quando consideradas as métricas de atraso e consumo energético.

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Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions

2021

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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Cited by 9 publications

References 16 publications

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Impacto de falhas transientes em memórias SRAM em nanotecnologia

Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions

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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Cited by 9 publications

References 16 publications

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Impacto de falhas transientes em memórias SRAM em nanotecnologia

Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions

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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation