A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

Shah, Jaspal Singh; Nairn, D.G.; Sachdev, Manoj

doi:10.1109/tns.2015.2429589

Cited by 30 publications

(13 citation statements)

References 25 publications

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“…In order to evaluate Huffman compression circuitry, suitable reported 65nm CMOS memory costs have been considered [27]- [29], from which it was established that 200pw for static power per bit and 3.3 um 2 area cost per bit-cell is a reasonable assumption. Huffman code-book area and static power cost can thus easily be estimated.…”

Section: ) a Basis For Huffman Power Estimationmentioning

confidence: 99%

A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit

Crispin-Bailey

Dai

Austin

2019

IEEE Trans. Biomed. Circuits Syst.

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0000-0003-0613-9698, Dai, Chengliang and Austin, James orcid.org/0000-0001-5762-8614 (2019) A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit. IEEE Transactions on Biomedical Circuits and Systems. pp.Abstract-A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel 'xor-log2-subband' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the 'simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um 2 . Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.

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Section: ) a Basis For Huffman Power Estimationmentioning

confidence: 99%

A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit

Crispin-Bailey

Dai

Austin

2019

IEEE Trans. Biomed. Circuits Syst.

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“…The 14T cell achieves better electrical performances and lower area cost, but the critical charge is by no means preferable to the 18T cell. Along came some other designs [7,8,9], however, the SEU hardening capabilities of these cells are not satisfactory enough.…”

Section: Introductionmentioning

confidence: 99%

A novel SEU hardened SRAM bit-cell design

Yang²,

Zhang

et al. 2017

IEICE Electron. Express

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An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

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“…Although supply voltage scaling has been proved to be the most effective method for energy saving [1,2,3,4,5,6], it will seriously deteriorate the read stability and write ability of the memory cell. Moreover, due to the process variations existing, the performance described above will be further deteriorated in low voltage, also in the future process nodes, which will result in the failure probability of read or write operations increasing [2,6,7,8,9,10]. Thus, the trade-off between performance and power should be considered.…”

Section: Introductionmentioning

confidence: 99%

“…1(a), is common utilized in industrial production [6]. During a read operation, the read disturbance will occur at the node "0" due to the voltage drop between the driver transistor and access transistor [1,6,9,10,11]. An effective workaround for this problem is increasing β ratio ð ðW=LÞ PD ðW=LÞ PG Þ [12] or increasing the tipping point of the cross-couple inverters.…”

Section: Introductionmentioning

confidence: 99%

“…To improve the write margin and read stability for conventional 6T SRAM, different types SRAM cell topologies as well as assist circuit has been proposed [1,2,3,6,7,8,9,10,11,12,13]. Decoupling the storage nodes with bit-line or lowering the voltage drop between the driver and access transistors is the efficient way to enhance read stability [11].…”

Section: Introductionmentioning

confidence: 99%

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Read/write margin enhanced 10T SRAM for low voltage application

Peng

Guan

et al. 2016

IEICE Electron. Express

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Abstract:The static random access memory (SRAM) is indispensable for high performance applications. With technology scaling, the device size as well as the operation supply voltage (VDD) is reduced. However, with the supply voltage decreasing, the performance of the conventional 6T SRAM is deteriorated seriously. In this letter, a symmetrical 10T SRAM with dramatically improved read stability and write ability is proposed. The simulation results indicate that, compared with the conventional 6T SRAM, the read static noise margin (RSNM) and write margin (WM) of the proposed 10T SRAM achieve 2.43× and 4.51× improvement, respectively, at a 0.8 V supply voltage in SMIC 65 nm technology. As a result, lower failure probability in access operations is expected. Moreover, the minimum supply voltage (VDD min ) of the proposed 10T SRAM achieves ∼0.32× compared with that of conventional 6T cell. Additionally, it also shows a better tolerance to the varying process variations.

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A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

Cited by 30 publications

References 25 publications

A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit

A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit

A novel SEU hardened SRAM bit-cell design

Read/write margin enhanced 10T SRAM for low voltage application

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