A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

“…Then, they were implemented at RTL level in Verilog-2001 (IEEE 1364) as technology-independent reusable IP-cores [1], using exactly the same optimized coding style for an equitable comparison. They are compile-time reconfigurable according to N and r. Reader is referred to [11], [19], and [12] for recoding tables used in equations (9), (10), and (13), respectively.…”

“…To increase the speed of the multiplier, most ancient processors employed radix-8, such as: Fchip [4], IBM S/390 [5], Alpha RISC [6], IA-32 [7] and AMDK7 [8]. While radix-16 is used only in the most recent Intel processors: 64 and IA-32 [9], and Itanium-Poulson [10].…”

A multi-format floating-point multiplier for power-efficient operations

“…As the wordlength becomes longer, the radix has been extended to radix-8 [4]- [6] and even radix-16 [7]. The advantage is that the PP reduction tree is shallower (faster and less power demanding) at expenses of a more complicate PP generation.…”

“…We chose radix-16 to limit the depth of the PP accumulation tree and save power. The unit was inspired by the implementation in the Intel Itanium FP-unit [7].…”

Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm

“…The small number of partial products is especially favorable when implementing a pipeline multiplier. Another study [2] proposes an Itanium processor that uses four clock cycles for the pipeline multiplier. In this case, large pipeline registers are required because the Wallace (or carry-save adder) tree is divided by the pipeline registers.…”