A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump by the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

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“…The switch can be located at the source of the current mirror MOS as shown in Fig. 3(c) [7]. M1 and M2 are in the saturation all the time.…”

Section: Single-ended Charge Pumpsmentioning

confidence: 99%

Design of high-performance CMOS charge pumps in phase-locked loops

Rhee

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

273

119

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“…The loop dynamically controls the supply voltage of DCO through an array of switched MOS resistors according to the frequency control word (FCW) generated by digital loop filter (DLF) [1], [2]. Besides, in order to prevent extrinsic noise from coupling to the oscillator supply voltage, some voltage-regulation techniques have been utilized, such as voltage regulator [3], and decoupled capacitors [2]. Unfortunately, in such a DPLL, the regulated DCO supply node actually is the frequency control node of the DCO, which means the regulator and decoupled capacitor is inside the DPLL loop.…”

Section: Introductionmentioning

confidence: 99%

A noise-insensitive high-resolution digitally controlled ring oscillator with multipoint-tuning technique

Han

Gai

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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An eight-phase digitally controlled ring oscillator that employs a multipoint-tuning technique is presented. The DCO fine-tuning is realized by multi-variable RC loads to improve frequency resolution and coupled-noise rejection by reducing DCO gain. With a set of rotating control logic circuits and eight DACs, the DCO achieves a minimum frequency quantization step of 55 kHz and noise sensitivity of 22 MHz/V. Implemented in a 0.13-μm CMOS process with a 1.2-V supply, the proposed ring-DCO is tuned by 24-bit frequency control word and operates from 1.76 to 3.74 GHz.

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“…Phase-locked loops are essential components in a wide variety of applications, from digital clock generation [1,2] to analogue integrated lock-in amplifiers [3] and wireless transceivers frequency synthesis [4,5]. A charge-pump (CP) PLL (Figure 1) is basically composed of a phase-frequency detector (PFD), a CP, a loop filter (LF), a voltage-controlled oscillator (VCO) and a frequency divider (FD).…”

Section: Introductionmentioning

confidence: 99%

On the simulation of fast settling charge pump PLLs up to fourth order

Guermandi

Franchi

Gnudi

2011

Circuit Theory & Apps

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SUMMARYIn this paper, we discuss three different models for the simulation of integer-N charge-pump phase-locked loops (PLLs), namely the continuous-time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time-domain model are introduced and the results are compared with those obtained by means of the s-domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems.

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A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

Cited by 94 publications

References 12 publications

Design of high-performance CMOS charge pumps in phase-locked loops

Design of high-performance CMOS charge pumps in phase-locked loops

A noise-insensitive high-resolution digitally controlled ring oscillator with multipoint-tuning technique

On the simulation of fast settling charge pump PLLs up to fourth order

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