A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly affect the accuracy of the calculation, the output frequency is continuously measured and frequency error is averaged to minimize those impacts. With 0.13um CMOS process, the proposed ADPLL operates at 2.7 GHz and achieves 0.35 us locking time while consuming 7.47mW.I.

No abstract

No abstract

No abstract

An eight-phase digitally controlled ring oscillator that employs a multipoint-tuning technique is presented. The DCO fine-tuning is realized by multi-variable RC loads to improve frequency resolution and coupled-noise rejection by reducing DCO gain. With a set of rotating control logic circuits and eight DACs, the DCO achieves a minimum frequency quantization step of 55 kHz and noise sensitivity of 22 MHz/V. Implemented in a 0.13-μm CMOS process with a 1.2-V supply, the proposed ring-DCO is tuned by 24-bit frequency control word and operates from 1.76 to 3.74 GHz.