A 336 Gbit/s Full-Parallel Window Decoder for Spatially Coupled LDPC Codes

Herrmann, Matthias; Wehn, Norbert; Thalmaier, Max; Fehrenz, Markus; Lehnigk-Emden, Timo; Alles, Matthias

doi:10.1109/eucnc/6gsummit51104.2021.9482457

Cited by 5 publications

(4 citation statements)

References 13 publications

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“…The column double-compact decoder was selected for the comparison as it achieves the highest throughput of the presented decoders. The FPWD in [12] is not listed in Table 2, as the results are similar to the column-compact decoder in Table 1.…”

Section: Implementation Resultsmentioning

confidence: 92%

“…In the course of the decoding, the processors exchange extrinsic messages. An implementation of a FPWD was presented in [12]. The decoder achieves a throughput of 336 Gbit/s in a 22 nm technology and is currently the fastest SC-LDPC decoder in the literature.…”

Section: State-of-the-art High-throughput Decodersmentioning

confidence: 99%

“…The decoders presented in the previous chapter, i.e., the RLPD, the RCPD, and the FPWD, are individual decoding solutions for SC-LDPC codes with the advantages and disadvantages discussed. In this chapter, we generalize several of the presented Herrmann and Wehn J Wireless Com Network (2022) 2022:90 state-of-the-art concepts, like the layered/compact window schedules [10] and overlapping decoding windows [12], and combine them with row-and column-wise decoding algorithms. This systematic approach leads to a new, more abstract perspective on state-of-the-art decoders.…”

Section: Proposed Pipeline Decoder Architecturesmentioning

confidence: 99%

“…For the processor design, we utilize the node-splitting concept [12] that was initially introduced for the check nodes in the FPWD and apply it to the variable nodes of a row-wise decoder and the check nodes of a column-wise decoder. Furthermore, the ondemand variable node activation (OVA) schedule for the row-wise decoding is extended to column-wise decoding.…”

Section: Processorsmentioning

confidence: 99%

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Beyond 100 Gbit/s Pipeline Decoders for Spatially Coupled LDPC Codes

Herrmann

Wehn

2022

J Wireless Com Network

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Low-density parity-check (LDPC) codes are a well-established class of forward error correction codes that provide excellent error correction performance for large code block sizes. However, for throughputs toward 1 Tbit/s, as expected for B5G systems, state-of-the-art LDPC soft decoders are restricted to short code block sizes of several hundred to thousands of bits due to routing congestion challenges, limiting the overall communications performance of the transmission system. Spatially coupled LDPC (SC-LDPC) codes and respective sliding window decoding methods show the potential to overcome these block size restrictions. However, in contrast to conventional LDPC codes little literature exists on the efficient hardware implementation of respective high-throughput decoders. In this work, we present the first in-depth investigation on the implementation of SC-LDPC decoders for throughputs beyond 100 Gbit/s. For an $$N=51328$$ N = 51328 , $$R=0.8$$ R = 0.8 terminated SC-LDPC code with sub-block size $$c=640$$ c = 640 and coupling width $$m_s=1$$ m s = 1 , we explore various design trade-offs, including row- and column-wise decoding, non-overlapping and overlapping window scheduling, and processor pipelining. To the best of our knowledge, this is the first description of a column-wise SC-LDPC decoding architecture in the literature. We complement the algorithmic investigation with the virtual silicon implementation of all presented decoders in a 22nm FD-SOI technology.

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Section: Implementation Resultsmentioning

confidence: 92%

Section: State-of-the-art High-throughput Decodersmentioning

confidence: 99%