A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm

Cernea, Raul; Pham, Long; Moogat, Farookh; Chan, Siu‐Wai; Le, Binh; Li, Yan; Tsao, Shouchang; Tseng, Tsun-Ming; Nguyen, Khanh; Li, J.; Hu, Jianghai; Park, Jong; Hsu, Cheng‐Hsing; Zhang, Fanglin; Kamei, Takeshi; Nasu, Hiroaki; Kliza, P.; Htoo, Khin; Lutze, J.; Yan, Dong; Higashitani, M.; Junhui, Yang; Lin, Hongwei; Sakhamuri, V.; Li, A.; Pan, Feng; Yadala, S.; Subodh, Taigor; Pradhan, K P; Lan, J.; Chan, James; Abe, T.; Fukuda, Yasushi; Mukai, Hideo; Kawakamr, K.; Liang, Chenju; Ip, T.; Chang, Shu-Fen; Lakshmipathi, J.; Huynh, Sharon; Pantelakis, D.; Mofidi, M.; Quader, K.

doi:10.1109/isscc.2008.4523236

Cited by 18 publications

(10 citation statements)

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“…a 159 mm 2 32-nm 32 Gb MLC Flash prototype [25] and 2. a 182 mm 2 56-nm 16 Gb MLC Flash prototype [26] We configure the chip as having two mats and a single subarray, following both [25,26]. We validate the area for both prototypes (since they do not report latency/energy values) and present the results in Table 9.…”

Section: Mlc Flash Validationmentioning

confidence: 99%

“…Table 2 summarizes the capabilities of DESTINY and compares them with those of CACTI and NVSim. We have compared the results obtained from DESTINY against several commercial and research prototypes [4,5,11,[15][16][17][18][19][20][21][22][23][24][25][26] to validate the newly-added memories, MLC and 3D models in DESTINY (Section 5). The modeling error has been observed to be less than 10% for most cases and less than 25% for all cases.…”

Section: Introductionmentioning

confidence: 99%

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DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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Section: Mlc Flash Validationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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“…In 2008, SanDisk introduced all-bit-line (ABL) architecture, 3 which uses a current-sensing scheme to connect each bit line to the sensing amplifier and a set of data latches.…”

Section: Architectural Improvementsmentioning

confidence: 99%

NAND Flash Memory: Challenges and Opportunities

Li¹,

Quader²

2013

Computer

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NAND flash offers a range of compelling benefits that will keep attracting mobile and enterprise application developers as engineers tackle the hard problems of scaling the technology to sub-20 nm.S ince NAND flash entered the market in 1987, its relatively low cost, compact size, quiet operation, speed, and ruggedness have made it a popular choice for mobile platforms such as smartphones and tablets, and it is replacing hard drives in many client and enterprise applications.In recent years, developers have successfully scaled 2D NAND flash to sub-20-nm technology, but further 2D NAND scalability will be a considerable challenge. Although new alternatives, such as 3D resistive RAM (ReRAM), are aiming to replace 2D NAND flash, NAND's entrenched position among nonvolatile storage options and the attractiveness of its low power consumption will make flash technology difficult to unseat. In enterprise storage, for example, flash solid-state drive (SSD) architectures are already leveraging massive parallelism to deliver high I/O operations per second for less power and cost than any currently available and practical technology.With these strong advantages, NAND can potentially supplant a portion of the dynamic RAM (DRAM) market, 1 and we expect future computing platforms to maximize NAND flash use in mobile, enterprise, and client product designs. Indeed, Gartner has forecast that units in all applications will triple over the next five years, with an average fourfold to fivefold capacity increase in SSDs over the same period. 2 The widespread adoption of flash will drive deeper cost reductions, which manufacturers will realize through increased scaling. As NAND flash devices scale down, application-specific systems management must maintain product reliability while continuing to address reduced endurance.Maintaining the reliability of NAND flash at 19 nm and beyond will also require breakthrough memory and system algorithms. Many efforts are in progress on more innovations in memory architecture, reliability, power, and high-speed I/O interfaces. Another body of work is focusing on the system design challenges of scaling 2D NAND flash, offering 3D NAND and other novel technologies as possible solutions. ArchitecturAl improvementsFor many years, half-bit-line (HBL), or shielded bit-line, architecture was the conventional NAND architecture in which, as Figure 1 shows, the system reads or writes only half the cells at a time to the word line. In 2008, SanDisk introduced all-bit-line (ABL) architecture, 3 which uses a current-sensing scheme to connect each bit line to the sensing amplifier and a set of data latches.ABL was a considerable improvement over HBL. In addition to doubling read and write throughput, ABL architecture has intrinsically better reliability. In HBL architecture, reading or programming stresses the same word line twice with high voltages; in ABL architecture, writing the same number of cells stresses the word line only once. The doubled high-voltage stress during program and read operations worsens m...

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“…This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1][2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation.…”

mentioning

confidence: 99%

“…Current-mode SA (CSA) achieves faster read speeds than VSA [1]. Cascodecurrent-load or resistive-divider-like CSAs (RD-CSAs) [1], [5], achieve sub100nA sensing, but require long BL settling times to achieve high-accuracy 1 ststage voltage difference. The inverter-offset-compensated SA (IOC-SA) [6] reduces the SA offset.…”

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confidence: 99%

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

Chang

Shen

Liu

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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Decreasing read cell current (I CELL ) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1-2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-I CELL NVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7× faster read speed than previous SAs for sensing small I CELL . A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logiccompatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA I CELL . Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing.Many small-I CELL NVMs employ voltage-mode SA (VSA) [2] with a long BL developing time to tolerate SA offset, at the cost of a reduced read speed. Current-mode SA (CSA) achieves faster read speeds than VSA [1]. Cascodecurrent-load or resistive-divider-like CSAs (RD-CSAs) [1], [5], achieve sub100nA sensing, but require long BL settling times to achieve high-accuracy 1 ststage voltage difference. The inverter-offset-compensated SA (IOC-SA) [6] reduces the SA offset. However, BL offset and BL settling time still limits its advantages with regard to VSA/CSA. In comparison with I CELL and a referencecurrent (I REF ), current-mirror CSA (CM-CSA) [7], has fast read speeds but cannot sense small I CELL due to its input-stage V TH mismatch. Figure 11.5.1 compares the concepts of CSB-SA with previous SAs. CSB-SA uses the same MOS device for current sampling and current-ratio amplifying. This enables V THindependent current sampling schemes for its differential I CELL and I REF inputs. This is significantly different from CM-CSA, using different MOS devices for current-mirroring or I-V conveying, which results in increased vulnerability to V THmismatch. In addition, CSB-SA uses sampled current to generate fast 1 st -stage voltage difference at its BL-decoupled small-load internal nodes. Unlike VSA or RD-CSA, which have to develop their 1 st -stage voltage on the heavy-load BL using continuous I CELL driving. IOC alleviates SA V TH -mismatch but with a complex multi-step V TH -nulling process and numerous switching devices. IOC also does not cancel the SA offset due to transistor width/length or T OX variations, and is still vulnerable to BL noise/C BL mismatch. In our CSB-SA, the sampled currents a...

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A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm

Cited by 18 publications

References 1 publication

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

NAND Flash Memory: Challenges and Opportunities

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

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