2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) 2016
DOI: 10.1109/vlsic.2016.7573533
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A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation

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Cited by 19 publications
(9 citation statements)
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“…If the method of increasing the signal power discussed in Section 3.1 is applied, there is room for reducing power consumption because the noise performance required to achieve the same SNR is alleviated [ 47 ]. Alternatively, a structure that removes the power of the pre-amplifier with a capacitance-to-digital (CDC) that connects the ADC directly to the sensor without using the pre-amplifier or a structure that eliminates overlapping circuits by combining the analog front-end pre-amplifier and ADC is suggested to reduce the power consumption of analog front-end circuits [ 48 , 49 , 50 , 51 , 52 ].…”
Section: Technical Issues Of the Capacitive Sensor Readout Systemmentioning
confidence: 99%
“…If the method of increasing the signal power discussed in Section 3.1 is applied, there is room for reducing power consumption because the noise performance required to achieve the same SNR is alleviated [ 47 ]. Alternatively, a structure that removes the power of the pre-amplifier with a capacitance-to-digital (CDC) that connects the ADC directly to the sensor without using the pre-amplifier or a structure that eliminates overlapping circuits by combining the analog front-end pre-amplifier and ADC is suggested to reduce the power consumption of analog front-end circuits [ 48 , 49 , 50 , 51 , 52 ].…”
Section: Technical Issues Of the Capacitive Sensor Readout Systemmentioning
confidence: 99%
“…Thus, minimizing C DAC and C p1 is beneficial to improve sensitivity, especially when C s is small. The calculation in (7) shows that the proposed CDC sensitivity depends on the parasitic capacitance C p1 , while this is not the case for the traditional switched-capacitor architectures (see [9]), which use an operational transconductance amplifier (OTA) to perform the charge transfer. As shown in Fig.…”
Section: Capacitive Bridge Analysismentioning
confidence: 99%
“…For another extreme case, when C s is much smaller than 2.5 pF, it is suggested to implement a comparable C r on-chip both for better sensitivity and less energy consumption, as the area overhead would be negligible. However, the sensitivity reduction caused by C DAC and C p1 becomes more relevant in this case, according to (7), and this will lead to performance degradation.…”
Section: Capacitive Bridge Analysismentioning
confidence: 99%
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