A 39-GHz Up- and Down-Conversion Mixer System in 65-nm CMOS for 5G Communication

Wang, Yiyang; Duan, Haipeng; He, Longbing; Wu, Xu; Wang, Dongming; Li, Lianming

doi:10.1109/gsmm53818.2022.9792340

Cited by 2 publications

(1 citation statement)

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“…As shown in Figure .2 the double balanced design consists of to single balanced mixers placed together. [6] The differential RF input is given to transconductance stage below which has to transistors and the switching stage has four transistors. Each time the switches change the position the small signal current direction changes through the load resistors and mixes with the LO signal, converting the current into voltage.…”

Section: Down Conversion Mixermentioning

confidence: 99%

A 0.2-2.2GHz CMOS mixer with noise cancellation

Ren

Liu²,

He³

2023

International Conference on Optoelectronic Materials and Devices (ICOMD 2022)

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A low noise active down converting mixer using quiescent current injection technique. The sinusoidal local oscillator signal is used to drive to avoid the noise superposition induced by the pulse ballast harmonics; the LC resonant structure is used to replace the resistance load of the traditional Gilbert unit to relieve the limitation of the charging and discharging of the parasitic capacitance of the tail node on the high-frequency operation of the circuit. The proposed mixer is implemented in a 65 nm CMOS process, with a working range of 0.2-2.2 GHz double-sideband noise figure with a maximum noise figure of 5 dB, and a minimum noise of 4.44 dB at the inflection point at 800 MHz. Working in the RF frequency band of 1GHz, the maximum voltage gain is 25dB, and the maximum 1dB compression point is -7.2dB, maximum IIP3 is 13 dB.

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Section: Down Conversion Mixermentioning

confidence: 99%