A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits

Abstract

Recent progress in the fabrication of three-dimensional integrated circuits has opened up the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical synthesis for three-dimensional integrated is substantially different from traditional planar integrated circuits due to the presence of additional constraints of placing circuit blocks in multiple die. To realize the full potential offered by three-dimensional integrated circuits, high-level synthesis of these circuits must take layout-related issues unique to 3-D technology into account during the synthesis process. We present a 3-D layout aware binding algorithm for high-level synthesis that tightly integrates the synthesis tasks of resource binding, assignment of modules to multiple die, 3-D floorplanning, and inter-die via minimization. Since floorplanning and resource binding are interdependent, the algorithm can significantly outperform traditional high-level synthesis flows that seperate these tasks. Compared to a traditional 3-D layout-unaware binding, experiments show that our approach can improve the total wirelength by 29% on average, while the longest netlength is reduced by 21%. In addition, the number of through-die via count is reduced by 27%. These optimizations are achieved with no penalty in chip area.

A Timing-driven Binding Algorithm for High-Level Synthesis of Three-dimensional Integrated Circuits

“…However, work on high-level synthesis systems aimed at 3-D layouts is still in its infancy. Previous work on high-level synthesis for 3-D integrated circuits include [16], [17], [18], and [19]. The authors of [16] and [17] formulate the high-level synthesis task and the assignment of RTL modules to various 3-D layers, as a Linear Programming problem that generates constraints to run a 3-D constraint-driven floorplanner.…”

“…In addition, LPbased approaches do not scale well with problem size and complexity. The methods presented in [18] and [19] tightly couples the high-level and floorplanning steps of the synthesis process, where the high-level synthesis decisions are guided by an integrated incremental floorplanner.…”

A resource binding technique for TSV number minimization in high-level synthesis of 3D ICs

“…Under the constraint of floorplaning criteria, Mukherjee and Vemuri [3][4] Proposed an integer linear programming formulation for simultaneous scheduling, binding, and layer assignment, and their objective function was composed of both the number of TSVs and the critical path length. Krishnan and Katkoori [5] proposed a framework to integrate the resource binding and floorplaning problems together in the 3D ICs structure. Lee et al [6][7] also proposed an integer linear programming model for high-level synthesis of 3D ICs, and guarantee to get the optimal solution for the number of TSVs under the resources and footprint area constrains.…”