In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that the register binding in high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Then, based on that observation, we formulate the problem of register binding for clock period minimization. Given a constraint on the number of registers, our objective is to find a minimumperiod register binding solution. Experimental data show that, in most benchmark circuits, the lower bound of the clock period can be achieved without any extra overhead on the number of registers.

The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure. In this paper, we present a linear program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) our paper is the first proof of showing that the time complexity of this problem is polynomial.

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