Register binding for clock period minimization

Huan, Shih-Hsu; Huang, Shih-Hsu; Cheng, Chun-Hua; Nieh, Yow-Tyng; Yu, Wei-Chieh

doi:10.1145/1146909.1147026

Cited by 17 publications

(12 citation statements)

References 11 publications

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“…Given a scheduled DFG and a resource binding solution, Huang et al [7] model the resulting hardware as a circuit graph, in which each vertex denotes a register and each directed edge denotes a data path. A special vertex called the host is introduced for the synchronization with primary inputs and primary outputs.…”

Section: Circuit Graph Of Resource Bindingmentioning

confidence: 99%

“…The min-period clock skew scheduling problem [5][6][7] is to find the smallest feasible clock period of a circuit graph. Conventionally, a constraint graph is used for solving the min-period clock skew scheduling problem in polynomial time complexity [6,7]. In the constraint graph, each vertex represents a register and each directed edge corresponds to a timing constraint.…”

Section: Min-period Clock Skew Schedulingmentioning

confidence: 99%

“…A data path from register R i to register R j in the circuit graph has two directed edges in the constraint graph: the setup constraint is modeled as a directed edge R j R i associated with a weight P-max(R i ,R j ), and the hold constraint is modeled as a directed edge R i R j associated with a weight min(R i ,R j ). From [6,7], we have the following lemma.…”

Section: Min-period Clock Skew Schedulingmentioning

confidence: 99%

“…Second, we use a conventional algorithm, e.g., left edge algorithm [4], to assign operations to functional units. Third, we use the register binding approach proposed in [7] to minimize the clock period. Fourth, the sleep transistor size of each functional unit (that is, the standby leakage current of each functional unit) is reduced according to its maximum allowable delay.…”

Section: Drawback Of Existing Flowmentioning

confidence: 99%

“…Conventionally, since the clock skew is assumed to be zero, the maximum allowable delay of each functional unit is definitely the target clock period; thus, there is no need to study this problem. However, in modern high-speed circuit design, the clock skew is often intentionally utilized to improve the circuit performance [5][6][7]. In this paper, we point out: due to the clock skews of registers, even though the operations are of the same type, they still have different maximum allowable delays.…”

Section: Introductionmentioning

confidence: 99%

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Timing driven power gating in high-level synthesis

Huang

Cheng

2009

2009 Asia and South Pacific Design Automation Conference

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The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work to draw up the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show: compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.

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Section: Circuit Graph Of Resource Bindingmentioning

confidence: 99%

Section: Min-period Clock Skew Schedulingmentioning

confidence: 99%

Section: Min-period Clock Skew Schedulingmentioning

confidence: 99%

Section: Drawback Of Existing Flowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Timing driven power gating in high-level synthesis

Huang

Cheng

2009

2009 Asia and South Pacific Design Automation Conference

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User Guided High Level Synthesis

Augé

Pétrot

High-Level Synthesis

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The User Guided Synthesis approach targets the generation of coprocessor under timing and resource constraints. Unlike other approaches that discover the architecture through a specific interpretation of the source code, this approach requires that the user guides the synthesis by specifying a draft of its data-path architecture. By providing this information, the user can get nearly the expected design in one shot instead of obtaining an acceptable design after an iterative process. Of course, providing a data-path draft limits its use to circuit designers. The approach requires three inputs: The first input is the description of the algorithm to be hardwired. It is purely functional, and does not contain any statement or pragma indicating cycle boundaries. The second input is a draft of the data-path on which the algorithm is to be executed. The third one is the target frequency of the generated hardware. The synthesis method is organized in two main tasks. The first task, called Coarse Grain Scheduling, targets the generation of a fully functional data-path. Using the functional input and the draft of the data-path (DDP), that basically is a directed graph whose nodes are functional or memorization operators and whose arcs indicate the authorized data-flow among the nodes, this task generates two outputs : - The first one is a RT level synthesizable description of the final coprocessor datapath, by mapping the instructions of the functional description on the DDP.- The second one is a coarse grain finite state machine in which each operator takes a constant amount of time to execute. It describes the flow of control without knowledge of the exact timing of the operators, but exhibits the parallelism among the instruction flow. The data-path is synthesized, placed and routed with back-end tools. After that, the timings such as propagation, set-up and hold-times, are extracted and the second task, called Fine Grain Scheduling, takes place. It basically performs the retiming of the Coarse Grain finite state machine taking into account the target frequency and the fine timings of the data-path implementation. Compared to the classical High Level Synthesis approaches, the User Guided Synthesis induces new algorithmic problems. For Coarse Grain Scheduling, it consists of finding whether an arithmetic and logic expression of the algorithmic input can be mapped on the given draft data-path or not, and when several mappings are found, to choose the one that maximizes the parallelism and minimizes the added resources. So the Coarse Grain Scheduling can be seen as a classical compiler, the differences being firstly that the target instruction set is not hardwired in the compiler but described fully or partially in the draft data-path, and secondly that a small amount of hardware can be added by the tools to optimize speed. For Fine Grain Scheduling, it consists of reorganizing the finite state machine to ensure that the data-path commands are synchronized with the execution delays of the operators they control. The fine ...

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Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis

Obata

Kaneko

2008

IEICE Transactions on Fundamentals of Electronics, Communicatio

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Register binding for clock period minimization

Cited by 17 publications

References 11 publications

Timing driven power gating in high-level synthesis

Timing driven power gating in high-level synthesis

User Guided High Level Synthesis

Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis

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