Clock period minimization with minimum delay insertion

Huang, Shih-Hsu; Cheng, Chun-Hua; Chang, Chia-Ling; Nieh, Yow-Tyng

doi:10.1145/1278480.1278720

Cited by 21 publications

(8 citation statements)

References 14 publications

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“…In [9], delay insertion methodology in clock skew scheduling is proposed. In [10], a linear programming approach is proposed to minimize the overall delay insertion while maintaining the minimum clock period. In order to mitigate the effect process variations on skew, multi-domain clock skew scheduling [11] is proposed.…”

Section: Introductionmentioning

confidence: 99%

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Liu

Salman

Sitik

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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Clock skew scheduling is a common and well known technique to improve the performance of sequential circuits by exploiting the mismatches in the data path delays. Existing clock skew scheduling techniques, however, cannot effectively consider heavily gated clock networks where a local clock tree exists between clock gating cells and registers. A methodology is proposed in this paper to efficiently achieve clock skew scheduling in circuits with gated clock networks. The methodology is implemented via both linear programming and constraint graph based approaches, and evaluated using the largest ISCAS'89 benchmark circuits with clock gating. The results demonstrate up to approximately 21% reduction in clock period while maintaining the power savings achieved by clock gating. A conventional design flow is used for the experiments, demonstrating the applicability of the proposed algorithms to automation.

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Section: Introductionmentioning

confidence: 99%

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Liu

Salman

Sitik

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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“…Hence, very accurate and high precise delay models in the order of picoseconds are vital to match current technology requirement. In various signalprocessing applications, synchronization of the signals is done by delaying a signal with respect to the other signal [1]. This requires a delay-introducing element capable of inserting desired amount of delay in order to match it with other signals.…”

Section: Introductionmentioning

confidence: 99%

A Compact Low Power High Frequency Pulse Generator

Dwivedi

Mehra

Tyagi

et al. 2015

2015 Fifth International Conference on Communication Systems and Network Technologies

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This paper proposes a compact, low power high frequency trigger pulse generator circuit. Delay-introducing circuit that can incorporate a certain amount of delay during signal processing while maintaining the signal integrity is utilized in the proposed design. This paper evaluates performance of various delay-introducing circuits in terms of different design matrices. Further, this paper exploits the low power consuming delay element to implement the proposed trigger pulse generator. The proposed design generates very high frequency pulses at the cost of negligible power consumption. The effectiveness of the proposed circuit is presented by producing ultra-thin pulses of pulse duration 92.35 ps while consuming power of only 1.502 ȝw. Extensive simulations are carried out on SPICE @ 16-nm predictive technology model to verify the proposed design.

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“…To do that, a set of constraints is given by setup-time and hold-time requirements, while the objective is to optimize either the clock period or the timing yield [1][2][3][4][5][6][7]. This problem can be formulated as a special kind of linear programming known as minimum cost-to-time ratio cycle problem, or minimum ratio cycle problem (MCR).…”

Section: Introductionmentioning

confidence: 99%