P+IPW N+/NW -l r l r i 0 . 8 . 0 0 . ! f . *. 0 t -. " ' . ! ' . A 180 nm generation logic technology has been developed with high performance 140 nm L G A~ transistors, six layers of aluminum interconnects and low-& SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power.The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiOz inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 pm2 6-T cell size have been built on this technology as a yield and reliability test vehicle.

We report a very high performance lOOnm gate length CMOS transistor structure operating at 1.2-1 SV. These transistors are incorporated in a 180nm logic technology generation. Various process enhancements are incorporated to significantly improve transistor current drive capability relative to the results published in [I]. Unique transistor features responsible for achieving high performance are described. NMOS and PMOS devices demonstrate drive current of 1.04 mA/pm and 0.46 mA/pm respectively at 1.5V and 3nA/pm IOFF. These are the best drive currents reported to date at fixed IOFF. They represents 10% drive current improvement for both NMOS and PMOS devices relative to the results published in Ref.[l] without any change in gate-oxide thickness. High performance is demonstrated down to 1.2V. Inverter delay of less than 10 psec is reported at 1.5V at very moderate IOFF values.

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