A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

Kawano, Motoharu; Uchiyama, S.; Egawa, Y.; Takahashi, Nobuaki; Kurita, Yasuo; Soejima, K.; Komuro, M.; Matsui, Satoshi; Shibata, Kayoko; Yamada, Junji; Ishino, M.; Ikeda, Hiroaki; Saeki, Yoshihiro; Kato, Osamu; Kikuchi, Hidekazu; Mitsuhashi, T.

doi:10.1109/iedm.2006.346849

Cited by 76 publications

(28 citation statements)

References 1 publication

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“…Fabrication of the TSV structures utilizes a standard via middle process [9][10][11]. Reactive ion etching (RIE) patterns the TSV structures to a depth of 50 µm.…”

Section: Design Of Experimentsmentioning

confidence: 99%

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Adamshick¹,

Carroll²,

Rao³

et al. 2014

PIER Letters

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Abstract-3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5 × 50 µm TSVs are manufactured using a via-mid integration scheme and characterized using S-parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.

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“…Fabrication of the TSV structures utilizes a standard via middle process [9][10][11]. Reactive ion etching (RIE) patterns the TSV structures to a depth of 50 µm.…”

Section: Design Of Experimentsmentioning

confidence: 99%

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Adamshick¹,

Carroll²,

Rao³

et al. 2014

PIER Letters

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“…TSVs are usually fabricated in a "regular" manner and grouped as bundles in many 3D-SIC designs [5,8], these regularly-placed TSVs can be naturally linked together to construct the proposed TSV redundancy architecture. In case that TSVs are not regularly placed, we can also map them into a logical TSV grid and apply our repair architecture (discussed later).…”

Section: A Overall Structurementioning

confidence: 99%

“…Early 3D-stacked IC (3D-SIC) products for CMOS image sensor camera modules are already in volume production [1,2]. 3D-stacked memory products were also announced by various companies recently [3][4][5]. Moreover, various techniques with massive use of TSVs have been proposed to fully exploit the benefits of this emerging technology(e.g., [6][7][8]).…”

Section: Introductionmentioning

confidence: 99%

On effective TSV repair for 3D-stacked ICs

Jiang

Eklow

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-3D-stacked ICs that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleaness of silicon dies, rendering prior TSV redundancy solutions less effective. To resolve this problem, we present a novel TSV repair framework, including a hardware architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, and the corresponding repair algorithm. By doing so, the manufacturing yield for 3D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

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“…Logic-to-memory data rates of 3 Gbps/pin or more has been studied for different applications [17]. Time domain simulations were performed for thin glass interposers with TPVs.…”

Section: Signal Transmission Line Simulationsmentioning

confidence: 99%

Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications

Kumar

Bandyopadhyay

Sukumaran

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10-30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than the 3D ICs with TSV stack approach being pursued widely, to achieve high bandwidth. This approach is referred to as interposer approach using ultra-thin glass or silicon with ultra-high I/O density interposers, which does not require TSVs in the logic IC in the 3D stack. This paper presents a comparative study, based on electrical modeling of the logic-to-memory signal path, in various current and emerging package configurations for use in smart mobile devices. Frequency and time domain analysis for each of these scenarios is performed using both chip and package-level models with varying interconnection dimensions. Simulated eye diagrams for the complete data paths in the thin glass interposer approach demonstrated more than 3 Gbps/pin data rate, similar to 3D ICs.

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A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

Cited by 76 publications

References 1 publication

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

On effective TSV repair for 3D-stacked ICs

Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications

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