On effective TSV repair for 3D-stacked ICs

Jiang, Jiang; Xu, Yang; Eklow,

doi:10.1109/date.2012.6176602

Cited by 66 publications

(51 citation statements)

References 26 publications

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“…Since we focus on the fault-tolerance structure with only one spare TSV, it is important to avoid grouping very close TSVs in the same structure [12], [25]. Therefore, we impose a minimum distance constraint, D min , to any two TSVs that can be in the same fault-tolerance structure, as suggested by [7] and [25].…”

Section: A Chip Yield Constraintmentioning

confidence: 99%

“…Due to traditional semiconductor manufacturing, TSV faults may have clustering effect rather than random distribution (e.g., warpage) [2], [12], [26]. Since we focus on the fault-tolerance structure with only one spare TSV, it is important to avoid grouping very close TSVs in the same structure [12], [25].…”

Section: A Chip Yield Constraintmentioning

confidence: 99%

“…1(b), the maximum distance between T 1 and T 2 depends on the slack of the signal that goes through T 1 . It also sets a lower bound on the distance between the TSVs in the same group due to the clustering effect of TSV faults (e.g., warpage) [2], [12], [26]. These distance constraints prevent us from randomly grouping TSVs to form a TSV fault-tolerance structure.…”

Section: Introductionmentioning

confidence: 99%

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Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Chen

Wen

Shi

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In 3-D integrated circuits, through silicon via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment, or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as a constrained graph decomposition problem. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 61%, compared with a seemingly more intuitive nearest-neighbor-based heuristic. Index Terms-Fault-tolerance, reliability, three dimensional integrated circuits (3-D IC), through silicon via (TSV).

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Section: A Chip Yield Constraintmentioning

confidence: 99%

Section: A Chip Yield Constraintmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Chen

Wen

Shi

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…1 shows possible locations of disconnection failures in 3D-IC technology with SEM images for better illustration. Accurate localization of disconnection along the channel can provide guidance for improvements in fabrication processes and contribute to advance the TSV recovery methods proposed in [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Frequency and time domain measurement of through-silicon via (TSV) failure

Jung

Kim

et al. 2012

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

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As a solution to limitlessly growing demand on miniaturization of electronic devices, through silicon via (TSV) based 3-dimensional integrated circuits (3D-IC) have brought another era of technology evolution. However, one of the remaining challenges to overcome is to increase the reliability of the products. Due to the instability of TSV fabrication process, different types of failure may be caused, affecting the performance of 3D-IC. TSV test method is essential for TSV based 3D-IC to be integrated in the products. One of the main failure types is disconnection failure in the channel. The point of defect not only has to be detected, but also has to be localized, so that appropriate channel is chosen to go through the recovery process. By measuring the fabricated test vehicles in frequency and time domain, the location of disconnection along the channel can be detected. S 11 and S 22 magnitudes are measured for frequency domain analysis. The degrees of decrease in two plots are compared to test how far the signals from each port travel before detecting the disconnection. Applying the similar idea, time domain measurement is analyzed with time-domain reflectometry (TDR) waveforms. The TDR waveforms from port 1 and port 2 are compared by their rising times, which depend on parasitic shunt capacitances within the channel. The values may be quantified for more precise TSV testing.

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“…Therefore, in order to accurately detect TSV disconnection, introduction of a new method that can surmount these problems, while maintaining accuracy is necessary, as accurate detection of TSV defects is necessary to further improve such TSV recovery methods proposed in [4][5].…”

Section: Introductionmentioning

confidence: 99%

Design of contactless wafer-level TSV connectivity testing structure using capacitive coupling

Kim¹,

Kim²,

Kim³

et al. 2013

2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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Driven by the abrupt miniaturization of mobile devices and demand for 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating multiple dies of various functions as a whole system. However, due to the instability in the TSV fabrication process, various types of disconnection defects can be resulted during fabrication steps, resulting in a severe decrease in the final chip yield as the number of TSVs and stacked dies increases. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure using capacitive coupling that can detect TSV disconnection defects on wafer-level. The proposed structure can detect the TSV disconnection by observing the change in the capacitance between adjacent TSVs, using only passive components such as metal pads and lines, without additional power consumption for the testing. Through time-and frequency-domain simulation results, such as transfer impedance and voltage waveforms, we verified that the proposed structure can successfully detect TSV defects, while overcoming the limitations of the conventional direct probing methods.

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On effective TSV repair for 3D-stacked ICs

Cited by 66 publications

References 26 publications

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Frequency and time domain measurement of through-silicon via (TSV) failure

Design of contactless wafer-level TSV connectivity testing structure using capacitive coupling

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