A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Wang, Dong; Guo, Xuan; Zhou, Lei; Wu, Danyu; Luan, Jian; Liu, Huasen; Wu, Jin; Liu, Xinyu

doi:10.3390/electronics8040464

Cited by 6 publications

(2 citation statements)

References 29 publications

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“…When all bits have been evaluated, the iterative process ends, leaving the final 16-bit digital output code. The usage of D flip-flops ensures accurate and dependable data by providing a synchronous and stable storage element for each bit [28].…”

Section: Design Of Sar Adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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Section: Design Of Sar Adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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“…Therefore, the use of digital processing of information requires the presence of a device that converts analog and digital signals into one another [1][2][3]. Analogtodigital and digitaltoanalog converters play the role of such a device [4].…”

Section: Introductionmentioning

confidence: 99%

Design principles of digital-to-analog conversion in information transformation

Agayev

Karimov

Mehdiyeva

et al. 2022

TAPR

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The object of study is digital-to-analog converter (DAC). The meaning of DAC, their design and control of various types of switches, as well as some logic elements that can act as a switch, as well as the principles of DAC operation based on various series, microcircuits were considered. The resistance of a 4-bit DAC circuit was calculated and, accordingly, the change in the output voltage when applying the corresponding combined input voltage was studied, and a timing diagram was accordingly developed. Using 1-state and toggle physical switches, schematics are established and side effects are learned. Ladder circuit established using R–2R type dividers as voltage dividers. The object of the research is to find and learn the most technologically advantageous concept in order to provide good communication between all equipments by transferring information from digital to analog in the industrial field as well as in other areas where automation is used. One of the biggest challenges in this research is to determine the smallest binary values. Before the use of electronic logic elements such as counters, bistable physical switches were used to create a break or connect state in the circuit, which caused additional energy and time loss or abrasion because of large voltages occur across the switches. The biggest issue was that when manufacturing integrated digital-to-analog converters, producing the right resistors with very different values is really difficult. As a result of this research, it is seen that the use of physical switches is unnecessary as a demand of today's modern technology, and integrated microcircuits are good to replace them. The programming of digital-to-analog converters on programmable hardware devices such as Arduino and Raspberry Pi were mentioned. If to predict the near future, digital-to-analog transmission will be realized only by only using logic elements, and this will change both their energy efficiency and size for the better.

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Design of IF-RF-Based Heterodyne Transmitter Using Current Steering DAC with 5.4 GHz Spur-Free Bandwidth

Kumar

Gupta

Bhadauria

2022

IETE Journal of Research

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A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Cited by 6 publications

References 29 publications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design principles of digital-to-analog conversion in information transformation

Design of IF-RF-Based Heterodyne Transmitter Using Current Steering DAC with 5.4 GHz Spur-Free Bandwidth

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A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Cited by 6 publications

References 29 publications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Design principles of digital-to-analog conversion in information transformation

Design of IF-RF-Based Heterodyne Transmitter Using Current Steering DAC with 5.4 GHz Spur-Free Bandwidth

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Product

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications