A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Abstract

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang-bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillatorbased two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER < 10 −12 ) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 mW power and achieves a recovered clock long-term jitter of 2.2 ps rms/24.0 pspp with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.Index Terms-Active repeater, automatic frequency acquisition, continuous-rate receivers, decouple jitter transfer (JTRAN)/jitter generation (JGEN), decouple JTRAN/jitter tolerance (JTOL), digital clock and data recovery (CDR), fractional-N phase-locked loop (PLL), high-speed serial link, jitter peaking, multiplying delaylocked loop, optical links, reference-less frequency-locked loop, supply regulator, wide-range digitally controlled oscillator (DCO).

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

“…A Clock-and-Data Recovery (CDR) circuit, which recovers the clock signal from the incoming random data sequences to retime the data, is one of the crucial building blocks in data communication devices [1], [2]. Though a Phase-Locked Loop (PLL) based architecture is often used for CDR [3]- [11], it usually requires long settling time to recover the target clock signal. In the applications that keep communicating for a long period of time, the performance overhead in this start-up is not of critical concern.…”

A wideband low-jitter PLL with an optimized Ring-VCO

“…Phase-Locked Loops (PLLs) are widely employed to generate high quality clocks for many applications such as mixers, analog-to-digital converters (ADCs), and I/O interfaces [1,2,3,4,5]. Jitter is a key characteristic to define the uncertainty of the sampling moments in ADCs and determine the bit error-rate in the system.…”

A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

“…Frequency dividers are a fundamental building block in many RF and mixed-signal high-speed systems, such as frequency synthesizers, I/Q signal generators, carrier recovery systems, SerDes systems, and time-interleaved data converters [1][2][3][4][5][6]. The evolution of technology enables faster and faster systems to be designed, with an increasing demand on higher frequency performance for all the blocks, however, on the other hand, there is a growing impulse to minimize the power consumption for these high frequency systems, to allow higher integration and to simplify packaging.…”