A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

Noguchi, Hidemi; Yoshida, N.; Uchida, Hiroyuki; Ozaki, M.; Kanemitsu, S.; Wada, S.

doi:10.1109/jssc.2008.2006227

Cited by 33 publications

(13 citation statements)

References 15 publications

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“…Improvements were made in [24,80] where both the edges and centre of the eye are used to quantify the opening of the eye. A two-dimensional EOM measures the dimension of the eye in both the vertical and horizontal directions [81][82][83][84]. Since the edge of the eye t c is determined by CDR, t H and t L can be chosen for the desired horizontal eye-opening using delay blocks.…”

Section: Eye-opening Adaptive Dfementioning

confidence: 99%

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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This study provides a comprehensive review of decision feedback equalisation (DFE) for multi-giga-bit-per-second (Gbps) data links. The state-of-the-art of DFE for multi-Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross-talk and their impact on data transmission are investigated. The fundamentals of both near-end and far-end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi-Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.

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Section: Eye-opening Adaptive Dfementioning

confidence: 99%

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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“…These errors can easily be detected by passing this slicer output, along with the fixed-threshold slicer output from the main data path, through an XOR gate. Counting the number of errors generated by each threshold step can be used to generate BER contours, which can then be used to select an optimum slicer threshold [9] or optimize equalizer tap coefficients [6].…”

Section: A Measuring the Received Pdfmentioning

confidence: 99%

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver

Dunwell

Carusone

2010

IEEE Custom Integrated Circuits Conference 2010

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A strategy for the adaptation of an equalizer and variable gain amplifier is presented. Both control signals are generated by examining the probability density function (PDF) of the received data, which is obtained from the DC output of an additional analog sampler at the equalizer output. This technique works to minimize the spreading of the PDF of the received signal while adding only minimal complexity and power consumption to the receiver design. The technique is demonstrated in a wireline receiver fabricated in 65-nm CMOS technology. Measured results show that the adaptation scheme functions correctly over both coax and PCB channels of varying lengths and at speeds ranging from 2 to 10 Gb/s.

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“…To achieve low power design, CMOS process is often used. However, the speed performance of CMOS is in the shade as compared to other high speed technologies such as SiGe [8], [9]. By lowering the clock frequency, it relaxes the speed limit caused by CMOS.…”

Section: Introductionmentioning

confidence: 99%

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Tan

Yeo

Boon

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18-CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.Index Terms-Charge Pump, Clock and Data Recovery (CDR), dual-loop, lock detector, Phase Detector (PD), quarter-rate architecture, 5-Gb/s.

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A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

Cited by 33 publications

References 15 publications

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

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