A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

Okaniwa, Y.; Tamura, Hirotaka; Kibune, Masaya; Yamazaki, Daisuke; Cheung, Taesik; Ogawa, J.; Tzartzanis, N.; Walker, William W.; Kuroda, Tadahiro

doi:10.1109/jssc.2005.852014

Cited by 46 publications

(15 citation statements)

References 12 publications

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“…There are many works about single event sensitivity in static comparator [7,8] which indicate SET is a great threat to the sampling result. However, the work about single event sensitivity in dynamic comparator is limited, though dynamic comparator is more attractive comparing to static comparator due to its faster speed profited from cross couple structure and lower power profited from the clock controlling [9,10].…”

Section: Introductionmentioning

confidence: 99%

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Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes

Chen

Huang

et al. 2015

IEICE Electron. Express

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Abstract:The radiation induced soft error of dynamic comparator for a 65 nm CMOS technology in 5 Gbps half-rate SerDes (serializer and deserializer) is evaluated using three-dimensional TCAD mixed-mode simulation. The sensitivity of MOSFET is simulated combined with the polarity of differential inputs and the working phases. Four types of single-event (SE) response are classified and the sensitivity grades are summarized. Our research presents that the NMOS of the cross-coupled inverter is the most sensitive.

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Section: Introductionmentioning

confidence: 99%

“…But his research is lack of attention on the polarity of differential inputs, the working phases and the SE relationship between striking moment and clock edge. Other studies on dynamic comparators focus on larger input swing, lower operating voltage, and so on which are not related to single event [12,13,14].…”

Section: Introductionmentioning

confidence: 99%

Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes

Chen

Huang

et al. 2015

IEICE Electron. Express

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“…Besides, low-voltage operation results in limited common-mode input range, which is important in many high-speed ADC architectures, such as flash ADCs. Many techniques, such as supply boosting methods [2], [3], techniques employing body-driven transistors [4], [5], current-mode design [6] and those using dual-oxide processes, which can handle higher supply voltages have been developed to meet the low-voltage design challenges. Boosting and bootstrapping are two techniques based on augmenting the supply, reference, or clock voltage to address input-range and switching problems.…”

Section: Introductionmentioning

confidence: 99%

High Speed and Low Power Double-Tail Comparator using Switching Transistor

Balla¹,

YKUNTAM²

2014

International Journal of Advanced Research in Computer and Comm

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Abstract:The high speed conversions are needed in the faster analog -to-digital converters. The accuracy of comparators is defined by its power consumption and speed. Many high speed ADCs, such as flash ADCs, require High speed, Low power comparators with small chip area. Conventional dynamic latched comparators suffer from low supply voltages especially when threshold voltage of the devices is not scaled at the same pace as the supply voltages of the modern CMOS process. The proposed comparator System has lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. In the dynamic Double tail comparator the simulation in a CMOS technology. In the Proposed dynamic Double tail comparator System both the power consumption and delay time will be significantly reduced. The maximum clock frequency of the proposed comparator can be reduced at modified supply voltages.

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“…Besides, low-supply-voltage operation results in limited commonmode input range, which is important for many high-speed ADC architectures, such as flash ADCs. Many techniques, such as techniques employing body-driven transistors [2], [3],current-mode design [4] , supply boosting methods [5], [6] and those using dual-oxide processes, which can handle higher supply voltages have been developed to undergo the low-voltage design challenges. Bootstrapping and boosting are two techniques based on raising the supply, reference, or clock voltage to mark input-range and switching problems.…”

mentioning

confidence: 99%