A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

Abstract

GaAs photoconductive switches have been integrated with two parallel 4-bit CMOS analog-to-digital (A/D) converter channels to demonstrate the time-interleaved sampling of wideband signals. The picosecond sampling aperture provided by lowtemperature-grown-GaAs metal-semiconductor-metal switches, in combination with low-jitter short-pulse lasers, enables the optically-triggered sampling of electrical signals with tens of gigahertz bandwidth at low to medium resolution. A pair of parallel sampling paths, one for sampling and the second for feedthrough cancellation, generate a differential held signal that is quantized by a low-input capacitance, high-speed flash A/D converter. Dynamic offset averaging is employed to improve converter linearity. An experimental time-interleaved two-channel A/D converter provides about 3.5 effective bits of resolution for inputs up to 40 GHz when tested at an optically-triggered sampling rate of 160 MHz. The sampling rate was limited by the available optical source. Each A/D converter channel operates up to a 640-MHz conversion rate, dissipates 70 mW of power, and occupies an area of 150 m 450 m in a 2.5-V, 0.25m CMOS technology.

Attosecond‐precision ultrafast photonics

“…Although the capability for higher sampling rates by time stretching and TDM-based time interleaving has been extensively studied, there has been no prior work that demonstrates photonic ADCs that fully exploit the timing jitter of optical pulse trains, which is far superior to that of electronic sampling clocks. To date, the best reported result of fully operating photonic ADCs for multi-GHz input signals is 3.5-ENOB resolution at a 40-GHz input frequency [116], which was mainly limited by the 100-fs timing jitter of the mode-locked laser used in that work. As discussed earlier, sub-10-fs-jitter pulse trains are now routinely generated from standard passively mode-locked fiber or solid-state lasers, and they have already been used for various timing and synchronization applications.…”

Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

“…Breaking the data conversion problem into multiple parallel sub-tasks is not a new concept, as exemplified by interleaved ADCs [19] and other random sampling architectures [20,21], which have existed in the literature and in practice for many years. Interleaved ADCs operate multiple ADCs in parallel with offset sampling times such that the resulting low-rate samples can be multiplexed back together into a higher effective sampling rate [22]. Although these architectures resolve the difficulty of designing fast ADCs, the high speed sample-and-hold circuits remain a challenge for high resolution Gsps ADCs.…”

A Jittered-Sampling Correction Technique for ADCs

“…However, photoconductive cell provide poor isolation between the input signal and the sampled value during 'off' mode. Nathawad et al [18] report a photonic sample and hold switch comprised of low-temperature GaAs metal-semiconductor-metal photocell that provide an on-resistance R 100 on < Ω and off-resistance R …”