A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices

Khwa, Win-San; Chiu, Yen-Cheng; Jhang, Chuan-Jia; Huang, Sheng-Po; Lee, Chun-Ying; Wen, Tai-Hao; Chang, Fu-Chun; Yu, S. M.; Lee, Tung-Yin; Chang, Meng‐Fan

doi:10.1109/isscc42614.2022.9731670

Cited by 63 publications

(11 citation statements)

References 4 publications

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“…The adoption of resistive memory elements limits possible implementations to NVM technologies only, since SRAM cells cannot provide ohmic behavior or work with analog voltages. NVM-based analog accelerators have been implemented with RRAM [94], [156]- [158], PCM [72], [159]- [161], STT-MRAM [103], [162] and FeFET devices [163].…”

Section: Fully Analog Circuitsmentioning

confidence: 99%

“…Alternatively, multilevel weights are obtained through bit-slicing techniques [156], [157], [162], differential implementations, or more complex cell structures, allowing several conductive levels to be obtained [159]. Also, a hybrid binary-multilevel accelerator has been proposed to achieve the best trade-off between accuracy and area efficiency [161]. Alongside the increase in the number of conductive levels, memory cells can contain a variable number of elements, for instance, 1T1R cell [95], [102], [164], differential 2T2R cell [158], or higher-complexity cells such as 8T4R [159].…”

Section: Fully Analog Circuitsmentioning

confidence: 99%

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In-Memory Computing for Machine Learning and Deep Learning

Lepri

Glukhov

Cattaneo

et al. 2023

IEEE J. Electron Devices Soc.

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In-memory computing (IMC) aims at executing numerical operations via physical processes, such as current summation and charge collection, thus accelerating common computing tasks including the matrix-vector multiplication. While extremely promising for memory-intensive processing such as machine learning and deep learning, the IMC design and realization must face significant challenges due to device and circuit nonidealities. This work provides an overview of the research trends and options for IMC-based implementations of deep learning accelerators with emerging memory technologies. The device technologies, the computing primitives, and the digital/analog/mixed design approaches are presented. Finally, the major device issues and metrics for IMC are discussed and benchmarked.

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Section: Fully Analog Circuitsmentioning

confidence: 99%

Section: Fully Analog Circuitsmentioning

confidence: 99%

In-Memory Computing for Machine Learning and Deep Learning

Lepri

Glukhov

Cattaneo

et al. 2023

IEEE J. Electron Devices Soc.

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“…These works can be classified based on the method in which Multiply-ACcumulate(MAC) is performed: current domain [16]- [20], charge domain [21]- [37] or fully digital [38] IMC. Additionally, some Non-CMOS [39]- [41] realisations of IMC have also been attempted. In both current and charge domain techniques, the MAC operation is performed within the memory in an analog manner and results in a voltage that is proportional to the MAC.…”

Section: Introductionmentioning

confidence: 99%

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

Sundar¹,

Viraraghavan²,

Vijayakumar³

2022

Preprint

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<p>In-Memory Computation(IMC) of Neural-Network(NN) inference is done by performing the Multiply-ACcumulate(MAC) operation in the analog domain. Parallelly digitising MAC voltages by fitting Analog to Digital Converters(ADCs) within dense memory-pitches is a fundamental challenge for IMC engines. IMC works thus far rely on clipping the MAC-PDF to reduce the dynamic range, reducing the per data-line(DL) ADC precision requirement. In this work, we show that the per-DL ADC precision can be reduced even further by focusing on quantising the input Conditioned MAC-PDF(CMPDF), which spans a sub-range in the total MAC-PDF. We demonstrate on hardware a technique to locate the CMPDF in one-shot by tracking its mean. We show that quantisation levels about the CMPDF mean can be skewed to only span the portion of CMPDF that yields positive ReLU inputs, provided MACs are implemented as complete sums. Compared to symmetrically spanning CMPDF, this requires 20% to 40% fewer references at iso-accuracy for the investigated neural network layers. Hardware measured results for Fully-Connected NN inference on MNIST yielded < 1% accuracy drop when MAC-voltages were quantised with 4 bit references about the CMPDF mean as compared to full-range 6 bit ADC sensing the MAC-voltages. MATLAB evaluation using 3.5 to 4.2 bit CMPDF quantisation for MNIST-FCNN, CIFAR-10 Resnet-20 and VGG-11 inference yielded < 1% accuracy drop as compared to full-range 6 to 7 bit MAC quantisation. </p>

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“…However, SRAM-based PIMs have the limitations of low bit density and large silicon area [1,2]. As an alternative, some studies have adopted next-generation nonvolatile memories, such as resistive RAM [8,9] or phase-change RAM [10]; however, these cannot easily be employed in general CMOS processes, and they require additional process steps that increase the manufacturing cost.…”

Section: Introductionmentioning

confidence: 99%

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Kim

Park

2022

Sensors

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This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

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A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices

Cited by 63 publications

References 4 publications

In-Memory Computing for Machine Learning and Deep Learning

In-Memory Computing for Machine Learning and Deep Learning

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

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