A 40 nm gate length n-MOSFET

Analytical Model of Tunneling Current by High Dielectrics and Study of High-k Gate Stack Structure

“…This potential is in turn determined by the amount of capacitive coupling between the transistor body and various electrodes.In long channel device the gate has exclusive control over the middle region of the body and can therefore effectively cut off the conduction. Though if the device length is reduced the section where the potential are controlled through source/drain,the electrodes eventually merge and the gate electrode will no longer be able to successfully block the current conduction [1][2][3].In order to improve the gate control the thickness of SiO 2 dielectric should be reduced which is shown in Fig.1. There are some reason to follow efficiency includes: (a) as MOSFET occupy small region so the price per transistor must be decreased (b) many transistor may be included in the circuit consequently it perform many multiple function (c) capacitance is decreased that decreases instant and influence needed to control MOSFET.…”

High Dielectric Constant Materials for Nanoscale Devices and Beyond

“…1. Although the operation of 40 nm gate length transistors was verified by experiments in 1993 20 it was still based on the SiO 2 gate insulator as high-k technology was not available at that time.…”

Fabrication of 40nm-gate MOSFETs by Nano-electron Beam Direct Writing.

“…Therefor, nanofabrication technology has been extensively investigated using Gaussian electron beams [1][2][3][4], because of its potential for the research of nanodevices such as single electron transistor. It is interesting that how small gate length MOSFETs can work practically [5][6][7][8], because the gate length becomes less than 0.1µm for 16Gbit DRAM. It is expected that such small devices will allow very high density integrated circuits, and high switching speeds with low power consumption.…”