Proceedings of the 2019 International Conference on Wireless Communication, Network and Multimedia Engineering (WCNME 2019) 2019
DOI: 10.2991/wcnme-19.2019.9
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A 40nm CMOS Ultra-Wideband Low Noise Amplifier Design

Abstract: An ultra-wideband low noise amplifier(LNA) based on the cascode configuration with resistive feedback is presented in this paper. A shunt-shunt feedback resistor and a pre-π matching network is employed to achieve wideband input impedance matching, and to enhance gain response and reduce noise for using a post-cascode inductor LP. In this paper, the SMIC 40nm CMOS process is used. The circuit simulation results show that S11 is lower than-10dB, and the gain S21 is around 10±2dB,and the NF is lower than 4.5dB i… Show more

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Cited by 4 publications
(7 citation statements)
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“…In Figure 1 b, a low-noise amplifier with resistance feedback is represented, simplified as a single-stage CS (common-source) amplifier. This configuration yields the following impedance and noise figure performance [ 8 ]. …”
Section: Lna Design Using Rc Feedback and Inductively Peaking Techniquementioning
confidence: 99%
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“…In Figure 1 b, a low-noise amplifier with resistance feedback is represented, simplified as a single-stage CS (common-source) amplifier. This configuration yields the following impedance and noise figure performance [ 8 ]. …”
Section: Lna Design Using Rc Feedback and Inductively Peaking Techniquementioning
confidence: 99%
“…However, for Cascode low-noise amplifiers intended for 5G NR, where bandwidth limitations exist, techniques for bandwidth extension become essential to achieve the desired bandwidth. Various techniques, such as distributed, coupled/resistive feedback, series peaking, double L-type matching network, and gm-boosting, are employed for this purpose [ 6 , 7 , 8 , 9 , 10 , 11 ]. In the case of the representative RC feedback technique, the bandwidth of the low-noise amplifier is determined by the transistor’s Ft (transition frequency) and the feedback loop.…”
Section: Introductionmentioning
confidence: 99%
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“…In this paper, a self-biased cascode structure was adopted, which introduces the AC voltage 𝑉 of the drain of M2 into the grid 𝑉 , and the bias voltage of 𝑉 is realized through 𝑅 -𝐶 . This structure can reduce one DC signal source while reducing the voltage difference between the M2 drain and grid and improving the output signal swing [9]. The size of the transistor is 4*75.…”
Section: Introductionmentioning
confidence: 99%
“…where the response of |𝑆 | includes two zero points. ꞷ 02 is as follows [7]: By expressing the current flowing into the R FB resistor as I x , the above equation can be obtained. C gs and g m are the gate-source capacitance and the transconductance of the transistor, respectively, and R L is the load resistance.…”
mentioning
confidence: 99%