A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology

Mishra, Jitendra Kumar; Srivastava, Harshit; Misra, Prasanna Kumar; Goswami, Manish

doi:10.1109/ises.2018.00011

Cited by 10 publications

(2 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The switching power consumption of each bit cell [13][14][15] in SRAM consumes a greater portion of power than the other power consumption, and thus cannot be ignored when considering the power consumption of the bit cells [16]. An improved SRAM bit cell that eliminates the switching of weak inverters was proposed in order to reduce switching power consumption.…”

Section: Proposed Sram Bit Cell Designmentioning

confidence: 99%

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

Kim,

Alnatsheh,

Yadav

et al. 2024

Electronics

View full text Add to dashboard Cite

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

show abstract

Section: Proposed Sram Bit Cell Designmentioning

confidence: 99%

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

Kim,

Alnatsheh,

Yadav

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…The sensing amplifier is a crucial element in terms of memory. Sense amplifiers (SAs) have developed into a distinct class of semiconductor memory circuits due to their quick evolution [23][24][25][26][27]. Since sensing does not damage the circuits, it is not necessary to feed the circuits with new data after sensing.…”

Section: Sense Amplifiersmentioning

confidence: 99%

Using Power Reduction Techniques, a Comparison of Differential and Latch Type Sense Amplifier Circuits

Tiwari¹,

Verma²,

Kirar³

2022

JFSA

View full text Add to dashboard Cite

Researchers have investigated several different sense amplifiers’ yield and other quantitative features. Amplification is required for various power-saving methods, including the sleep transistor, the sleep stack, the sleepy keeper, and others. This study aims to evaluate how much energy is consumed by the many different sense amplifier topologies. Simulations have shown that adopting a sleep transistor approach can significantly reduce the amount of power lost even while operating at 1.2V.

show abstract

Comparative Study of Latch Type and Differential Type Sense Amplifier Circuits Using Power Reduction Techniques

Agrawal

2021

Communications in Computer and Information Science

View full text Add to dashboard Cite

A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology

Cited by 10 publications

References 16 publications

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

Using Power Reduction Techniques, a Comparison of Differential and Latch Type Sense Amplifier Circuits

Comparative Study of Latch Type and Differential Type Sense Amplifier Circuits Using Power Reduction Techniques

Contact Info

Product

Resources

About