2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
DOI: 10.1109/vlsit.2002.1015435
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A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

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Cited by 6 publications
(1 citation statement)
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“…Table V shows the comparative analysis of CMOS inverter at optimized value with the previous literatures. Propagation delay is observed lesser for proposed device as compared to Celik et al, 19 Rodoni et al 20 and Panda et al 21 However, noise margin is lesser for proposed device which can be trade-off with the propagation delay.…”
Section: Cmos Inverter-in the Digital Circuit Design Cmos Inverter Ismentioning
confidence: 68%
“…Table V shows the comparative analysis of CMOS inverter at optimized value with the previous literatures. Propagation delay is observed lesser for proposed device as compared to Celik et al, 19 Rodoni et al 20 and Panda et al 21 However, noise margin is lesser for proposed device which can be trade-off with the propagation delay.…”
Section: Cmos Inverter-in the Digital Circuit Design Cmos Inverter Ismentioning
confidence: 68%