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In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

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In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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