Perspective of Buried Oxide Thickness Variation on Triple Metal-Gate (TMG) Recessed-S/D FD-SOI MOSFET

Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET

“…SOI devices were made to effectively suppress the SCEs but still, SOI devices are not able to completely free from SCE [15]. The short channel effects mainly found in SOI devices are kink effect (at high drain voltage, for transistor operating above threshold), self heating mechanism as the buried oxide makes a good thermal isolation to Silicon substrate, drain current overshoot, latch effect which is observed when SOI MOSFET operates at subthreshold region and complexity in formation of thin Silicon films [18][19][20].…”

Polycrystalline silicon PhC cavities for CMOS on-chip integration

“…However, beside SOI higher cost compared to bulk Si wafers, this approach severely hinders the performance of electronics as, at telecom wavelengths, low-loss optical confinement in the photonic waveguides requires at least a 1 µm thick buried oxide, while SOI transistors need very thin buried oxide (100 nm or lower) for thermal dissipation and electrostatic effects. Thick buried oxide means that transistor gate lengths must be longer than 100 nm and transistor density decreases 6 , 7 , considerably limiting processors performance and scalability. Some effort has also been directed towards the front-end integration of waveguides on bulk-Si 8 – 10 and thin-SOI substrates 11 , 12 , but these techniques always comprise the fabrication steps involving the modification of the silicon electronics layer.…”